Monden; Junji

Patent Applications and Registrations

Patent applications and USPTO patent grants for Monden; Junji.The latest application filed is for "semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error".

Company Profile

0.12.8

Monden; Junji - Kanagawa N/A JP
Monden; Junji - Kawasaki JP
Monden; Junji - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error Grant 8,471,336 - Furuta , et al. June 25, 2	2013-06-25
Semiconductor Integrated Circuit Including Transistor Having Diffusion Layer Formed At Outside Of Element Isolation Region For Preventing Soft Error App 20120241860 - Furuta; Hiroshi ; et al.	2012-09-27
Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error Grant 8,169,037 - Furuta , et al. May 1, 2	2012-05-01
Semiconductor integrated circuit having latch circuit applied changeable capacitance and method thereof Grant 8,044,694 - Monden October 25, 2	2011-10-25
Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region Grant 7,973,371 - Furuta , et al. July 5, 2	2011-07-05
Semiconductor integrated circuit device Grant 7,808,056 - Furuta , et al. October 5, 2	2010-10-05
Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit Grant 7,743,289 - Furuta , et al. June 22, 2	2010-06-22
Semiconductor memory device Grant 7,688,109 - Monden , et al. March 30, 2	2010-03-30
Semiconductor integrated circuit having latch circuit applied changeable capacitance and method thereof App 20100019839 - Monden; Junji	2010-01-28
Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error App 20090289311 - Furuta; Hiroshi ; et al.	2009-11-26
Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region App 20090091964 - Furuta; Hiroshi ; et al.	2009-04-09
Semiconductor memory device App 20080309372 - Monden; Junji ; et al.	2008-12-18
Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit App 20080256403 - Furuta; Hiroshi ; et al.	2008-10-16
Semiconductor integrated circuit device App 20080099857 - Furuta; Hiroshi ; et al.	2008-05-01
Integrated circuit apparatus Grant 7,274,616 - Furuta , et al. September 25, 2	2007-09-25
Integrated circuit apparatus App 20060164905 - Furuta; Hiroshi ; et al.	2006-07-27
Semiconductor memory device operable in burst mode and method of controlling the same Grant 5,848,023 - Kato , et al. December 8, 1	1998-12-08
Semiconductor memory device with error self-correction system starting parity bit generation/error correction sequences only when increase of error rate is forecasted Grant 5,546,410 - Ando , et al. August 13, 1	1996-08-13
Internal synchronous static RAM Grant 5,047,984 - Monden September 10, 1	1991-09-10

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.