Molson; Philippe

Patent Applications and Registrations

Patent applications and USPTO patent grants for Molson; Philippe.The latest application filed is for "methods and apparatus for performing design for debug via protocol interface".

Company Profile

0.26.1

Molson; Philippe - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and apparatus for performing design for debug via protocol interface Grant 10,866,278 - Molson December 15, 2	2020-12-15
Methods And Apparatus For Performing Design For Debug Via Protocol Interface App 20190219635 - Molson; Philippe	2019-07-18
Apparatus and methods for multiple-channel direct memory access Grant 9,684,615 - Nguyen , et al. June 20, 2	2017-06-20
High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry Grant 9,552,323 - Finan , et al. January 24, 2	2017-01-24
High-level language code sequence optimization for implementing programmable chip designs Grant 9,329,847 - Pritchard , et al. May 3, 2	2016-05-03
Partial reconfiguration using configuration transaction layer packets Grant 9,257,987 - Molson February 9, 2	2016-02-09
Modular direct memory access system Grant 9,053,093 - Nguyen , et al. June 9, 2	2015-06-09
DSP design system level power estimation Grant 8,661,396 - Plofsky , et al. February 25, 2	2014-02-25
High-level language code sequence optimization for implementing programmable chip designs Grant 8,578,356 - Pritchard , et al. November 5, 2	2013-11-05
DSP design system level power estimation Grant 8,402,419 - Plofsky , et al. March 19, 2	2013-03-19
Scheduling optimization of aliased pointers for implementation on programmable chips Grant 8,291,396 - Lau , et al. October 16, 2	2012-10-16
Method and apparatus for providing protected intellectual property Grant 8,200,472 - Molson , et al. June 12, 2	2012-06-12
Embedded logic analyzer functionality for system level environments Grant 7,991,606 - D'Souza , et al. August 2, 2	2011-08-02
DSP design system level power estimation Grant 7,882,457 - Plofsky , et al. February 1, 2	2011-02-01
High-level language code sequence optimization for implementing programmable chip designs Grant 7,873,953 - Pritchard , et al. January 18, 2	2011-01-18
Finite impulse response (FIR) filter compiler for estimating cost of implementing a filter Grant 7,865,347 - San , et al. January 4, 2	2011-01-04
Method and apparatus for providing protected intellectual property Grant 7,676,355 - Molson , et al. March 9, 2	2010-03-09
System level simulation models for hardware modules Grant 7,509,246 - Molson , et al. March 24, 2	2009-03-24
Finite impulse response (FIR) filter compiler Grant 7,480,603 - San , et al. January 20, 2	2009-01-20
Method and apparatus for enabling waveform display in a system design model Grant 7,360,189 - Molson April 15, 2	2008-04-15
Bit accurate hardware simulation in system level simulators Grant 7,318,014 - Molson , et al. January 8, 2	2008-01-08
Method and apparatus for simulating a hybrid system with registered and concurrent nodes Grant 7,181,384 - Riggs , et al. February 20, 2	2007-02-20
DSP design system level power estimation Grant 7,143,368 - Plofsky , et al. November 28, 2	2006-11-28
Finite impulse response (FIR) filter compiler Grant 7,110,927 - San , et al. September 19, 2	2006-09-19
Interleaver-deinterleaver megacore Grant 6,634,009 - Molson , et al. October 14, 2	2003-10-14

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