Moharil; Rahul Sharad

Patent Applications and Registrations

Patent applications and USPTO patent grants for Moharil; Rahul Sharad.The latest application filed is for "generating a test case micro generator during processor design verification and validation".

Company Profile

0.4.6

Moharil; Rahul Sharad - Maharashtra IN
Moharil; Rahul Sharad - Nagpur IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for generating fast instruction and data interrupts for processor design verification and validation Grant 8,099,559 - Choudhury , et al. January 17, 2	2012-01-17
System and method for using resource pools and instruction pools for processor design verification and validation Grant 7,752,499 - Choudhury , et al. July 6, 2	2010-07-06
System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation Grant 7,739,570 - Bag , et al. June 15, 2	2010-06-15
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation Grant 7,647,539 - Bussa , et al. January 12, 2	2010-01-12
Generating a Test Case Micro Generator During Processor Design Verification and Validation App 20090307468 - Choudhury; Shubhodeep Roy ; et al.	2009-12-10
System and Method for Efficiently Handling Interrupts App 20090070570 - Choudhury; Shubhodeep Roy ; et al.	2009-03-12
System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation App 20090070768 - Choudhury; Shubhodeep Roy ; et al.	2009-03-12
System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation App 20090070546 - Choudhury; Shubhodeep Roy ; et al.	2009-03-12
System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation App 20090024873 - Bag; Sandip ; et al.	2009-01-22
System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation App 20090024892 - Bussa; Vinod ; et al.	2009-01-22

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