MOHAN; Sundararajarao

Patent Applications and Registrations

Patent applications and USPTO patent grants for MOHAN; Sundararajarao.The latest application filed is for "blockchain machine network acceleration engine".

Company Profile

5.44.14

MOHAN; Sundararajarao - Sunnyvale CA
Mohan; Sundararajarao - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Blockchain Machine Network Acceleration Engine App 20220138178 - YANG; Ji ; et al.	2022-05-05
Blockchain Machine Compute Acceleration Engine App 20220131704 - JAVAID; Haris ; et al.	2022-04-28
Integration of a programmable device and a processing system in an integrated circuit package Grant 11,024,583 - Lesea , et al. June 1, 2	2021-06-01
Migrating virtual machines between compute systems by transmitting programmable logic accelerator state Grant 10,740,146 - Mohan A	2020-08-11
Integration Of A Programmable Device And A Processing System In An Integrated Circuit Package App 20200161247 - LESEA; Austin H. ; et al.	2020-05-21
Integration of a programmable device and a processing system in an integrated circuit package Grant 10,573,598 - Lesea , et al. Feb	2020-02-25
Striped direct memory access circuit Grant 10,474,599 - Mohan Nov	2019-11-12
Integration Of A Programmable Device And A Processing System In An Integrated Circuit Package App 20190096813 - Lesea; Austin H. ; et al.	2019-03-28
Migrating Accelerators Between Compute Systems App 20180232254 - Mohan; Sundararajarao	2018-08-16
Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit Grant 9,880,966 - Hwang , et al. January 30, 2	2018-01-30
Compilation of system designs Grant 9,805,152 - Carrillo , et al. October 31, 2	2017-10-31
Automatic implementation of a customized system-on-chip Grant 9,652,570 - Kathail , et al. May 16, 2	2017-05-16
Multiprocessor system with performance control based on input and output data rates Grant 9,557,795 - Sabih , et al. January 31, 2	2017-01-31
Method and apparatus for adaptively tuning an integrated circuit Grant 9,444,497 - Mohan , et al. September 13, 2	2016-09-13
Compilation of HLL code with hardware accelerated functions Grant 9,223,921 - Carrillo , et al. December 29, 2	2015-12-29
Hardware and software cosynthesis performance estimation Grant 9,147,024 - Kathail , et al. September 29, 2	2015-09-29
Software debugging of synthesized hardware Grant 8,775,986 - Mohan , et al. July 8, 2	2014-07-08
Automatic generation of a data transfer network Grant 8,762,916 - Kathail , et al. June 24, 2	2014-06-24
Integrated circuit providing improved feed back of a signal Grant 8,327,200 - Mohan December 4, 2	2012-12-04
Event-driven simulation of IP using third party event-driven simulators Grant 7,721,090 - Deepak , et al. May 18, 2	2010-05-18
Method and system for function acceleration using custom instructions Grant 7,676,661 - Mohan , et al. March 9, 2	2010-03-09
Method and system for designing a multiprocessor Grant 7,310,594 - Ganesan , et al. December 18, 2	2007-12-18
Configurable logic element with expander structures Grant 7,248,073 - New , et al. July 24, 2	2007-07-24
Method and apparatus for providing self-implementing hardware-software libraries Grant 7,243,330 - Ganesan , et al. July 10, 2	2007-07-10
Configurable logic element with expander structures App 20070035328 - New; Bernard J. ; et al.	2007-02-15
Configurable logic element with expander structures Grant 7,145,360 - New , et al. December 5, 2	2006-12-05
Softpal implementation and mapping technology for FPGAs with dedicated resources Grant 7,111,273 - Ganesan , et al. September 19, 2	2006-09-19
Configurable logic element with expander structures App 20050062498 - New, Bernard J. ; et al.	2005-03-24
Configurable logic element with expander structures Grant 6,847,229 - New , et al. January 25, 2	2005-01-25
Configurable logic element with expander structures App 20040032283 - New, Bernard J. ; et al.	2004-02-19
Configurable logic element with expander structures Grant 6,630,841 - New , et al. October 7, 2	2003-10-07
Configurable logic block for PLD with logic gate for combining output with another configurable logic block Grant 6,603,332 - Kaviani , et al. August 5, 2	2003-08-05
Method for implementing large multiplexers with FPGA lookup tables Grant 6,505,337 - Wittig , et al. January 7, 2	2003-01-07
Logic/memory circuit having a plurality of operating modes Grant 6,501,296 - Wittig , et al. December 31, 2	2002-12-31
Hetergeneous method for determining module placement in FPGAs Grant 6,457,164 - Hwang , et al. September 24, 2	2002-09-24
Configurable logic element with expander structures App 20020125910 - New, Bernard J. ; et al.	2002-09-12
System and method of computation in a programmable logic device using virtual instructions Grant 6,421,817 - Mohan , et al. July 16, 2	2002-07-16
Configurable logic block for PLD with logic gate for combining output with another configurable logic block App 20020079921 - Kaviani, Alireza S. ; et al.	2002-06-27
Configurable lookup table for programmable logic devices Grant 6,400,180 - Wittig , et al. June 4, 2	2002-06-04
Configurable logic element with expander structures Grant 6,396,302 - New , et al. May 28, 2	2002-05-28
Delay optimized mapping for programmable gate arrays with multiple sized lookup tables Grant 6,336,208 - Mohan , et al. January 1, 2	2002-01-01
Configurable logic element with expander structures App 20010045844 - New, Bernard J. ; et al.	2001-11-29
Logic/memory circuit having a plurality of operating modes App 20010043082 - Wittig, Ralph D. ; et al.	2001-11-22
Configurable lookup table for programmable logic devices App 20010030555 - Witting, Ralph D. ; et al.	2001-10-18
Context-sensitive self implementing modules Grant 6,292,925 - Dellinger , et al. September 18, 2	2001-09-18
Method for specifying routing in a logic module by direct module communication Grant 6,260,182 - Mohan , et al. July 10, 2	2001-07-10
On-chip self-modification for PLDs Grant 6,255,849 - Mohan July 3, 2	2001-07-03
Heterogeneous method for determining module placement in FPGAs Grant 6,243,851 - Hwang , et al. June 5, 2	2001-06-05
Methods and media for utilizing symbolic expressions in circuit modules App 20010001881 - Mohan, Sundararajarao ; et al.	2001-05-24
Method for constraining circuit element positions in structured layouts Grant 6,237,129 - Patterson , et al. May 22, 2	2001-05-22
FPGA modules parameterized by expressions Grant 6,216,258 - Mohan , et al. April 10, 2	2001-04-10
Method for implementing large multiplexers with FPGA lookup tables Grant 6,191,610 - Wittig , et al. February 20, 2	2001-02-20
FPGA configurable logic block with multi-purpose logic/memory circuit Grant 6,150,838 - Wittig , et al. November 21, 2	2000-11-21
Method for implementing large multiplexers with FPGA lookup tables Grant 6,118,300 - Wittig , et al. September 12, 2	2000-09-12
Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM Grant 6,091,263 - New , et al. July 18, 2	2000-07-18
Method for configuring FPGA memory planes for virtual hardware computation Grant 6,047,115 - Mohan , et al. April 4, 2	2000-04-04