Moench; Jerry D.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Moench; Jerry D..The latest application filed is for "multi-ported register cell with randomly accessible history".
- Moench; Jerry D. - Austin TX
- Moench; Jerry D. - Tempe AZ
| Patent | Date |
|---|---|
| Multi-ported register cell with randomly accessible history Grant 7,366,032 - Huber , et al. April 29, 2 | 2008-04-29 |
| Memory array with global bitline domino read/write scheme Grant 7,355,881 - Dankert , et al. April 8, 2 | 2008-04-08 |
| Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit Grant 7,315,054 - Moench , et al. January 1, 2 | 2008-01-01 |
| Microprocessor including bank-pipelined cache with asynchronous data blocks Grant 7,124,236 - Tan , et al. October 17, 2 | 2006-10-17 |
| Method and apparatus for sensing a programming state of fuses Grant 6,670,843 - Moench , et al. December 30, 2 | 2003-12-30 |
| Interlaced layout configuration for differential pairs of interconnect lines Grant 5,581,126 - Moench December 3, 1 | 1996-12-03 |
| Logic allocator for a programmable logic device Grant 5,485,104 - Agrawal , et al. January 16, 1 | 1996-01-16 |
| Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices Grant 5,457,409 - Agrawal , et al. October 10, 1 | 1995-10-10 |
| High speed centralized switch matrix for a programmable logic device Grant 5,436,514 - Agrawal , et al. * July 25, 1 | 1995-07-25 |
| Switch matrix multiplexers Grant 5,307,352 - Moench April 26, 1 | 1994-04-26 |
| Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix Grant 5,225,719 - Agrawal , et al. * July 6, 1 | 1993-07-06 |
| Multiple array high performance programmable logic device family Grant 5,015,884 - Agrawal , et al. May 14, 1 | 1991-05-14 |
| Flexible, programmable cell array interconnected by a programmable switch matrix Grant 4,963,768 - Agrawal , et al. October 16, 1 | 1990-10-16 |
| Partial memory selection using a programmable decoder Grant 4,633,429 - Lewandowski , et al. December 30, 1 | 1986-12-30 |
| Serial data mode circuit for a memory Grant 4,484,308 - Lewandowski , et al. November 20, 1 | 1984-11-20 |
| Substrate bias voltage regulator Grant 4,401,897 - Martino, Jr. , et al. August 30, 1 | 1983-08-30 |
| Substrate bias regulator Grant 4,356,412 - Moench , et al. October 26, 1 | 1982-10-26 |
| Differential capacitive buffer Grant 4,291,246 - Martino, Jr. , et al. September 22, 1 | 1981-09-22 |
| ROM Storage location having more than two states Grant 4,272,830 - Moench June 9, 1 | 1981-06-09 |
| Speed-up circuit Grant 4,250,410 - Moench , et al. February 10, 1 | 1981-02-10 |
| Quiet column decoder Grant 4,200,917 - Moench April 29, 1 | 1980-04-29 |
| Digital predecoding system Grant 4,194,130 - Moench March 18, 1 | 1980-03-18 |
| Static storage technique for four transistor IGFET memory cell Grant 4,023,149 - Bormann , et al. May 10, 1 | 1977-05-10 |
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