Modi; Primit
Patent Applications and Registrations
Patent applications and USPTO patent grants for Modi; Primit.The latest application filed is for "bias control circuit with distributed architecture for memory cells".
- Modi; Primit - San Jose CA
- Modi; Primit - Fremont CA
| Patent | Date |
|---|---|
| Bias control circuit with distributed architecture for memory cells Grant 10,424,358 - Sundaresan , et al. Sept | 2019-09-24 |
| Duty cycle correction scheme for complementary signals Grant 10,284,182 - Modi , et al. | 2019-05-07 |
| Bias Control Circuit With Distributed Architecture For Memory Cells App 20180358069 - SUNDARESAN; Supraja ; et al. | 2018-12-13 |
| Duty Cycle Correction Scheme For Complementary Signals App 20180175834 - Modi; Primit ; et al. | 2018-06-21 |
| Bulk modulation scheme to reduce I/O pin capacitance Grant 9,792,994 - Modi , et al. October 17, 2 | 2017-10-17 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 