loadpatents
name:-0.085407018661499
name:-0.0087389945983887
name:-0.00046086311340332
Moat; Kent D. Patent Filings

Moat; Kent D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Moat; Kent D..The latest application filed is for "method and apparatus for nested instruction looping using implicit predicates".

Company Profile
0.9.10
  • Moat; Kent D. - Winfield IL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and apparatus for nested instruction looping using implicit predicates
Grant 7,945,768 - Essick, IV , et al. May 17, 2
2011-05-17
Method and apparatus for battery-aware dynamic bandwidth allocation for groups of wireless sensor nodes in a wireless sensor network
Grant 7,801,079 - Saidi , et al. September 21, 2
2010-09-21
Method and Apparatus for Nested Instruction Looping Using Implicit Predicates
App 20090307472 - Essick IV; Raymond B. ;   et al.
2009-12-10
Memory address generation with non-harmonic indexing
Grant 7,502,909 - Moat , et al. March 10, 2
2009-03-10
Method and Apparatus for Reducing Buffer Overflow Exploits by Computer Viruses
App 20080250499 - Moat; Kent D. ;   et al.
2008-10-09
Method And Apparatus For Battery-aware Dynamic Bandwidth Allocation For Groups Of Wireless Sensor Nodes In A Wireless Sensor Network
App 20080211666 - Saidi; Ali ;   et al.
2008-09-04
Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
Grant 7,415,601 - May , et al. August 19, 2
2008-08-19
Component interconnect with self-clocking data
Grant 7,289,528 - Moat , et al. October 30, 2
2007-10-30
Dataflow graph compression for power reduction in a vector processor
Grant 7,290,122 - May , et al. October 30, 2
2007-10-30
Queuing cache for vectors with elements in predictable order
Grant 7,246,203 - Moat , et al. July 17, 2
2007-07-17
Bus filter for memory address translation
Grant 7,219,209 - Essick, IV , et al. May 15, 2
2007-05-15
Memory address generation with non-harmonic indexing
App 20070083729 - Moat; Kent D. ;   et al.
2007-04-12
Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values
Grant 7,100,019 - Norris , et al. August 29, 2
2006-08-29
Queuing cache for vectors with elements in predictable order
App 20060112229 - Moat; Kent D. ;   et al.
2006-05-25
Component interconnect with self-clocking data
App 20050047430 - Moat, Kent D. ;   et al.
2005-03-03
Bus filter for memory address translation
App 20050050297 - Essick, Raymond B. IV ;   et al.
2005-03-03
Dataflow graph compression for power reduction in a vector processor
App 20050050300 - May, Philip E. ;   et al.
2005-03-03
Method and apparatus for elimination of prolog and epilog instructions in a vector processor
App 20040128473 - May, Philip E. ;   et al.
2004-07-01
Partitioned vector processing
App 20040117595 - Norris, James M. ;   et al.
2004-06-17

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