Miyayama; Yoshiyuki

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miyayama; Yoshiyuki.The latest application filed is for "high-performance, superscalar-based computer system with out-of-order instruction execution".

Company Profile

0.46.21

Miyayama; Yoshiyuki - Nagano-ken JP
Miyayama; Yoshiyuki - Santa Clara CA
Miyayama; Yoshiyuki - Suwa JP
Miyayama, Yoshiyuki - Sawa-shi JP
Miyayama, Yoshiyuki - Suwa-shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for handling load and/or store operations in a superscalar microprocessor Grant 8,019,975 - Brashears , et al. September 13, 2	2011-09-13
High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution Grant 7,941,635 - Nguyen , et al. May 10, 2	2011-05-10
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,739,482 - Nguyen , et al. June 15, 2	2010-06-15
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,721,070 - Nguyen , et al. May 18, 2	2010-05-18
System and method for translating non-native instructions to native instructions for processing on a host processor Grant 7,664,935 - Coon , et al. February 16, 2	2010-02-16
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 7,555,632 - Nguyen , et al. June 30, 2	2009-06-30
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,487,333 - Nguyen , et al. February 3, 2	2009-02-03
High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution App 20090019261 - NGUYEN; Le Trong ; et al.	2009-01-15
System and Method for Translating Non-Native Instructions to Native Instructions for Processing on a Host Processor App 20080162880 - Coon; Brett ; et al.	2008-07-03
System and method for translating non-native instructions to native instructions for processing on a host processor Grant 7,343,473 - Coon , et al. March 11, 2	2008-03-11
High-performance, superscalar-based computer system with out-of-order instruction execution App 20070106878 - Nguyen; Le Trong ; et al.	2007-05-10
High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution App 20070101103 - Nguyen; Le Trong ; et al.	2007-05-03
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,162,610 - Nguyen , et al. January 9, 2	2007-01-09
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution App 20060149925 - Nguyen; Le Trong ; et al.	2006-07-06
Microcomputer, electronic equipment, and debugging system Grant 7,065,678 - Miyayama , et al. June 20, 2	2006-06-20
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 7,028,161 - Nguyen , et al. April 11, 2	2006-04-11
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,986,024 - Nguyen , et al. January 10, 2	2006-01-10
System and method for handling load and/or store operations in a superscalar microprocessor App 20050283591 - Brashears, Cheryl Senter ; et al.	2005-12-22
System and method for handling load and/or store operations in a superscalar microprocessor Grant 6,965,987 - Senter Brashears , et al. November 15, 2	2005-11-15
System and method for translating non-native instructions to native instructions for processing on a host processor App 20050251653 - Coon, Brett ; et al.	2005-11-10
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,959,375 - Nguyen , et al. October 25, 2	2005-10-25
System and method for translating non-native instructions to native instructions for processing on a host processor Grant 6,954,847 - Coon , et al. October 11, 2	2005-10-11
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,948,052 - Nguyen , et al. September 20, 2	2005-09-20
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,941,447 - Nguyen , et al. September 6, 2	2005-09-06
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,934,829 - Nguyen , et al. August 23, 2	2005-08-23
Microcomputer, electronic equipment, and debugging system Grant 6,922,795 - Miyayama , et al. July 26, 2	2005-07-26
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,915,412 - Nguyen , et al. July 5, 2	2005-07-05
Microcomputer, electronic equipment, and debugging system App 20050102579 - Miyayama, Yoshiyuki ; et al.	2005-05-12
Method for improving pin compatibility in microcomputer emulation equipment Grant 6,799,157 - Kudo , et al. September 28, 2	2004-09-28
Microcomputer, electronic equipment, and debugging system App 20040153812 - Miyayama, Yoshiyuki ; et al.	2004-08-05
System and method for handling load and/or store operations in a superscalar microprocessor App 20040128487 - Brashears, Cheryl Senter ; et al.	2004-07-01
High performance, superscalar-based computer system with out-of-order instruction execution App 20040093483 - Nguyen, Le Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order instruction execution App 20040093482 - Nguyen, Le-Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order instruction execution App 20040093485 - Nguyen, Le Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order intstruction execution App 20040054872 - Nguyen, Le Trong ; et al.	2004-03-18
Microcomputer, electronic equipment, and debugging system Grant 6,665,821 - Miyayama , et al. December 16, 2	2003-12-16
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,647,485 - Nguyen , et al. November 11, 2	2003-11-11
System and method for translating non-native instructions to native instructions for processing on a host processor App 20030084270 - Coon, Brett ; et al.	2003-05-01
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030079113 - Nguyen, Le Trong ; et al.	2003-04-24
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030070060 - Nguyen, Le Trong ; et al.	2003-04-10
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030056086 - Nguyen, Le Trong ; et al.	2003-03-20
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030056087 - Nguyen, Le Trong ; et al.	2003-03-20
High-performance, superscalar-based computer system with out-of-order instruction execution App 20020029328 - Nguyen, Le Trong ; et al.	2002-03-07
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution App 20020016903 - Nguyen, Le Trong ; et al.	2002-02-07
Data processing circuit with target instruction and prefix instruction Grant 6,308,258 - Kubota , et al. October 23, 2	2001-10-23
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 6,282,630 - Nguyen , et al. August 28, 2	2001-08-28
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,272,619 - Nguyen , et al. August 7, 2	2001-08-07
System and method for translating non-native instructions to native instructions for processing on a host processor Grant 6,263,423 - Coon , et al. July 17, 2	2001-07-17
High performance, superscalar-based computer system with out-of-order instruction execution Grant 6,256,720 - Nguyen , et al. July 3, 2	2001-07-03
Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same Grant 6,249,167 - Oguchi , et al. June 19, 2	2001-06-19
Multiple sum-of-products circuit and its use in electronic equipment and microcomputers Grant 6,233,596 - Kubota , et al. May 15, 2	2001-05-15
Data processing circuit with target instruction and prefix instruction Grant 6,167,505 - Kubota , et al. December 26, 2	2000-12-26
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,128,723 - Nguyen , et al. October 3, 2	2000-10-03
High performance, superscalar-based computer system with out-of-order instruction execution Grant 6,038,654 - Nguyen , et al. March 14, 2	2000-03-14
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 6,038,653 - Nguyen , et al. March 14, 2	2000-03-14
System and method for handling load and/or store operations in a superscalar microprocessor Grant 5,987,593 - Senter , et al. November 16, 1	1999-11-16
Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions Grant 5,983,334 - Coon , et al. November 9, 1	1999-11-09
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 5,832,292 - Nguyen , et al. November 3, 1	1998-11-03
High-performance superscalar-based computer system with out-of-order instruction execution Grant 5,689,720 - Nguyen , et al. November 18, 1	1997-11-18
System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor Grant 5,619,666 - Coon , et al. April 8, 1	1997-04-08
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 5,560,032 - Nguyen , et al. September 24, 1	1996-09-24
Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor Grant 5,546,552 - Coon , et al. August 13, 1	1996-08-13
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 5,539,911 - Nguyen , et al. July 23, 1	1996-07-23
RISC microprocessor architecture implementing fast trap and exception state Grant 5,481,685 - Nguyen , et al. January 2, 1	1996-01-02
RISC microprocessor architecture implementing fast trap and exception state Grant 5,448,705 - Nguyen , et al. September 5, 1	1995-09-05
System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer Grant 5,438,668 - Coon , et al. August 1, 1	1995-08-01
System and method for resetting a microprocessor system Grant 5,297,287 - Miyayama , et al. March 22, 1	1994-03-22

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