loadpatents
name:-0.0016019344329834
name:-0.3480749130249
name:-0.0090439319610596
Miyatake; Hideshi Patent Filings

Miyatake; Hideshi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miyatake; Hideshi.The latest application filed is for "memory circuit".

Company Profile
0.22.0
  • Miyatake; Hideshi - Itami JP
  • Miyatake; Hideshi - Hyogo JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Memory circuit
Grant 5,295,094 - Miyatake March 15, 1
1994-03-15
Semiconductor memory device having bit lines capable of partial operation
Grant 5,189,639 - Miyatake February 23, 1
1993-02-23
Dynamic random access memory with read-write signal of shortened duration
Grant 5,079,748 - Miyatake , et al. * January 7, 1
1992-01-07
Dynamic semiconductor memory device having improved voltage read-out
Grant 5,020,031 - Miyatake May 28, 1
1991-05-28
Semiconductor dynamic random access memory with relaxed pitch condition for sense amplifiers and method of operating the same
Grant 4,980,864 - Fukuhama , et al. December 25, 1
1990-12-25
Dynamic random access memory
Grant 4,945,517 - Miyatake , et al. July 31, 1
1990-07-31
Dynamic random access memory device and operating method therefor
Grant 4,916,666 - Fukuhama , et al. April 10, 1
1990-04-10
Semiconductor memory device having on-chip error check and correction functions
Grant 4,903,268 - Hidaka , et al. February 20, 1
1990-02-20
Semiconductor memory device with an improved multi-bit test mode
Grant 4,899,313 - Kumanoya , et al. February 6, 1
1990-02-06
Circuit for generating a boosted signal for a word line
Grant 4,896,297 - Miyatake , et al. January 23, 1
1990-01-23
Semiconductor memory device with address transition detection and timing control
Grant 4,843,596 - Miyatake , et al. June 27, 1
1989-06-27
Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block
Grant 4,837,747 - Dosaka , et al. June 6, 1
1989-06-06
MDS decoder circuit with high voltage suppression of a decoupling transistor
Grant 4,811,304 - Matsuda , et al. March 7, 1
1989-03-07
Semiconductor memory device
Grant 4,760,559 - Hidaka , et al. July 26, 1
1988-07-26
Dummy word line driving circuit for a MOS dynamic RAM
Grant 4,757,476 - Fujishima , et al. July 12, 1
1988-07-12
Dynamic RAM with active pull-up circuit
Grant 4,736,343 - Hidaka , et al. April 5, 1
1988-04-05
Semiconductor memory device
Grant 4,730,320 - Hidaka , et al. March 8, 1
1988-03-08
Semiconductor storage unit with I/O bus precharging and equalization
Grant 4,722,074 - Fujishima , et al. January 26, 1
1988-01-26
Semiconductor memory device
Grant 4,675,850 - Kumanoya , et al. June 23, 1
1987-06-23
Semiconductor memory device with a laser programmable redundancy circuit
Grant 4,658,379 - Fujishima , et al. April 14, 1
1987-04-14
Semiconductor memory device
Grant 4,586,167 - Fujishima , et al. April 29, 1
1986-04-29
Semiconductor memory device
Grant 4,575,825 - Ozaki , et al. March 11, 1
1986-03-11

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