loadpatents
name:-0.0029041767120361
name:-0.0079340934753418
name:-0.0004580020904541
Miura; Hirotomo Patent Filings

Miura; Hirotomo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miura; Hirotomo.The latest application filed is for "method of making a polycide interconnection layer having a silicide film formed on a polycrystal silicon for a semiconductor device".

Company Profile
0.8.2
  • Miura; Hirotomo - Tokyo JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of making a polycide interconnection layer having a silicide film formed on a polycrystal silicon for a semiconductor device
Grant 6,800,911 - Miura October 5, 2
2004-10-05
Multi-level type nonvolatile semiconductor memory device
Grant 6,649,542 - Miura , et al. November 18, 2
2003-11-18
Method of making a polycide interconnection layer having a silicide film formed on a polycrystal silicon for a semiconductor device
App 20030205769 - Miura, Hirotomo
2003-11-06
Multi-level type nonvolatile semiconductor memory device
Grant 6,605,839 - Miura , et al. August 12, 2
2003-08-12
Method For Fabricating A Semiconductor Device Having A Impurity Layer Disposed Between A Non-doped Silicon Film And High Melting-point Metal Film For Reducing Solid State Reaction Between Said High Melting-point Metal Film And Polycrystal Silicon Film
Grant 6,596,567 - Miura July 22, 2
2003-07-22
Method of making multi-level type non-volatile semiconductor memory device
Grant 6,596,590 - Miura , et al. July 22, 2
2003-07-22
Multi-level type nonvolatile semiconductor memory device
App 20020145161 - Miura, Hirotomo ;   et al.
2002-10-10
Multi-level type nonvolatile semiconductor memory device
Grant 6,285,596 - Miura , et al. September 4, 2
2001-09-04
Semiconductor structure provided with a polycide interconnection layer having a silicide film formed on a polycrystal silicon film
Grant 6,208,003 - Miura March 27, 2
2001-03-27
Input protective circuit having a diffusion resistance layer
Grant 5,932,917 - Miura August 3, 1
1999-08-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed