| Patent | Date |
|---|
Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
Grant 5,123,097 - Joyce , et al. June 16, 1 | 1992-06-16 |
Apparatus and method for address translation of non-aligned double word virtual addresses
Grant 5,051,894 - Phillips , et al. September 24, 1 | 1991-09-24 |
Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
Grant 4,785,398 - Joyce , et al. November 15, 1 | 1988-11-15 |
Least recently used replacement level generating apparatus
Grant 4,783,735 - Miu , et al. November 8, 1 | 1988-11-08 |
Arithmetic logic unit with outputs indicating invalid computation results caused by invalid operands
Grant 4,608,659 - Bradley , et al. August 26, 1 | 1986-08-26 |
Data processing system having synchronous bus wait/retry cycle
Grant 4,495,571 - Staplin, Jr. , et al. January 22, 1 | 1985-01-22 |
Program counter stacking method and apparatus for nested subroutines and interrupts
Grant 4,488,227 - Miu , et al. December 11, 1 | 1984-12-11 |
Microprogrammed system having hardware interrupt apparatus
Grant 4,484,271 - Miu , et al. November 20, 1 | 1984-11-20 |
Data processing system having centralized bus priority resolution
Grant 4,459,665 - Miu , et al. July 10, 1 | 1984-07-10 |
Microprogrammed system having single microstep apparatus
Grant 4,387,423 - King , et al. June 7, 1 | 1983-06-07 |
Data processing system having data entry backspace character apparatus
Grant 4,383,295 - Miller , et al. May 10, 1 | 1983-05-10 |
Data processing system having centralized data alignment for I/O controllers
Grant 4,321,665 - Shen , et al. March 23, 1 | 1982-03-23 |
Data processing system having centralized memory refresh
Grant 4,317,169 - Panepinto, Jr. , et al. February 23, 1 | 1982-02-23 |
Data processing system having data multiplex control apparatus
Grant 4,300,193 - Bradley , et al. November 10, 1 | 1981-11-10 |
Data processing system having multiple common buses
Grant 4,300,194 - Bradley , et al. November 10, 1 | 1981-11-10 |
Data processing system having direct memory access bus cycle
Grant 4,293,908 - Bradley , et al. October 6, 1 | 1981-10-06 |
Data processing interrupt apparatus having selective suppression control
Grant 4,218,739 - Negi , et al. August 19, 1 | 1980-08-19 |
Data processing system self-test enabling technique
Grant 4,127,768 - Negi , et al. November 28, 1 | 1978-11-28 |
Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus
Grant 4,050,097 - Miu , et al. September 20, 1 | 1977-09-20 |
Data processing system utilizing control store unit and push down stack for nested subroutines
Grant 3,909,797 - Goss , et al. September 30, 1 | 1975-09-30 |
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