Mitra; Sujoy

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mitra; Sujoy.The latest application filed is for "consolidation potential score model".

Company Profile

0.7.2

Mitra; Sujoy - Mumbai IN
Mitra; Sujoy - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Consolidation Potential Score Model App 20120010925 - Mitra; Sujoy	2012-01-12
Hetergeneous method for determining module placement in FPGAs Grant 6,457,164 - Hwang , et al. September 24, 2	2002-09-24
Method for structured layout in a hardware description language Grant 6,430,732 - Hwang , et al. August 6, 2	2002-08-06
Context-sensitive self implementing modules Grant 6,292,925 - Dellinger , et al. September 18, 2	2001-09-18
Method for specifying routing in a logic module by direct module communication Grant 6,260,182 - Mohan , et al. July 10, 2	2001-07-10
Heterogeneous method for determining module placement in FPGAs Grant 6,243,851 - Hwang , et al. June 5, 2	2001-06-05
Methods and media for utilizing symbolic expressions in circuit modules App 20010001881 - Mohan, Sundararajarao ; et al.	2001-05-24
Method for constraining circuit element positions in structured layouts Grant 6,237,129 - Patterson , et al. May 22, 2	2001-05-22
FPGA modules parameterized by expressions Grant 6,216,258 - Mohan , et al. April 10, 2	2001-04-10

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