Mitra; Joydeep

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mitra; Joydeep.The latest application filed is for "directed self-assembly-aware layout decomposition for multiple patterning".

Company Profile

0.9.5

Mitra; Joydeep - Okemos MI
Mitra; Joydeep - Austin TX
Mitra; Joydeep - Hyderabad IN
Mitra; Joydeep - Las Cruces NM
Mitra; Joydeep - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Linear optimal power flow system and method Grant 10,296,988 - Mitra	2019-05-21
Tool employing homotopy-based approaches in finding the controlling unstable equilibrium point in the electric power grid Grant 10,097,000 - Mitra , et al. October 9, 2	2018-10-09
Directed Self-Assembly-Aware Layout Decomposition For Multiple Patterning App 20170220729 - Pikus; Fedor ; et al.	2017-08-03
Directed self-assembly-aware layout decomposition for multiple patterning Grant 9,652,581 - Pikus , et al. May 16, 2	2017-05-16
Display screen with graphical user interface Grant D782,496 - Contreras , et al. March 28, 2	2017-03-28
Display screen with a dashboard for a user interface Grant D776,130 - Contreras , et al. January 10, 2	2017-01-10
Directed Self-Assembly-Aware Layout Decomposition For Multiple Patterning App 20160292345 - Pikus; Fedor ; et al.	2016-10-06
Generating guiding patterns for directed self-assembly Grant 9,330,228 - Robles , et al. May 3, 2	2016-05-03
Tool Employing Homotopy-based Approaches In Finding The Controlling Unstable Equilibrium Point In The Electric Power Grid App 20160041232 - MITRA; Joydeep ; et al.	2016-02-11
Generating Guiding Patterns For Directed Self-Assembly App 20150227676 - Robles; Juan Andres Torres ; et al.	2015-08-13
Linear Optimal Power Flow System and Method App 20150051744 - MITRA; Joydeep	2015-02-19
Standby generator integration system Grant 7,180,210 - Jorgenson , et al. February 20, 2	2007-02-20
System and method for performing assertion-based analysis of circuit designs Grant 6,591,402 - Chandra , et al. July 8, 2	2003-07-08
Hierarchical coupling noise analysis for submicron integrated circuit designs Grant 6,449,753 - Aingaran , et al. September 10, 2	2002-09-10

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