Mitchell; Peter H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mitchell; Peter H..The latest application filed is for "method of making integrated circuit chip utilizing oriented carbon nanotube conductive layers".

Company Profile

1.42.42

Mitchell; Peter H. - Jericho VT
Mitchell; Peter H - Jericho VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of cleaving a single crystal substrate parallel to its active planar surface and method of using the cleaved daughter substrate Grant 10,589,445 - Furukawa , et al.	2020-03-17
Method of making integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,989,222 - Furukawa , et al. August 2, 2	2011-08-02
Immersion lithography with equalized pressure on at least projection optics component and wafer Grant 7,889,317 - Furukawa , et al. February 15, 2	2011-02-15
Methods and structures for promoting stable synthesis of carbon nanotubes Grant 7,851,064 - Furukawa , et al. December 14, 2	2010-12-14
Vertical carbon nanotube field effect transistors and arrays Grant 7,829,883 - Furukawa , et al. November 9, 2	2010-11-09
Method of Making Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers App 20100273298 - Furukawa; Toshiharu ; et al.	2010-10-28
Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby Grant 7,820,502 - Furukawa , et al. October 26, 2	2010-10-26
Integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,786,583 - Furukawa , et al. August 31, 2	2010-08-31
Vertical nanotube semiconductor device structures and methods of forming the same Grant 7,691,720 - Furukawa , et al. April 6, 2	2010-04-06
Method of forming a dual gated FinFET gain cell Grant 7,674,674 - Furukawa , et al. March 9, 2	2010-03-09
Sub-lithographic imaging techniques and processes Grant 7,585,614 - Furukawa , et al. September 8, 2	2009-09-08
Method of forming a dual gated FinFET gain cell Grant 7,566,613 - Furukawa , et al. July 28, 2	2009-07-28
Methods for forming a wrap-around gate field effect transistor Grant 7,560,347 - Furukawa , et al. July 14, 2	2009-07-14
Vertical carbon nanotube transistor integration Grant 7,535,016 - Furukawa , et al. May 19, 2	2009-05-19
Shallow trench isolation fill by liquid phase deposition of SiO.sub.2 Grant 7,525,156 - Hakey , et al. April 28, 2	2009-04-28
Method for making integrated circuit chip having carbon nanotube composite interconnection vias Grant 7,473,633 - Furukawa , et al. January 6, 2	2009-01-06
Dual Gated Finfet Gain Cell App 20080261363 - Furukawa; Toshiharu ; et al.	2008-10-23
Method for making integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,439,081 - Furukawa , et al. October 21, 2	2008-10-21
Methods for forming a wrap-around gate field effect transistor Grant 7,435,653 - Furukawa , et al. October 14, 2	2008-10-14
Vertical Nanotube Semiconductor Device Structures And Methods Of Forming The Same App 20080227264 - Furukawa; Toshiharu ; et al.	2008-09-18
Wrap-around Gate Field Effect Transistor App 20080206937 - Furukawa; Toshiharu ; et al.	2008-08-28
SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 App 20080197448 - Hakey; Mark Charles ; et al.	2008-08-21
Immersion Lithography With Equalized Pressure On At Least Projection Optics Component And Wafer App 20080165335 - Furukawa; Toshiharu ; et al.	2008-07-10
Methods And Structures For Promoting Stable Synthesis Of Carbon Nanotubes App 20080160312 - Furukawa; Toshiharu ; et al.	2008-07-03
Immersion lithography with equalized pressure on at least projection optics component and wafer Grant 7,385,673 - Furukawa , et al. June 10, 2	2008-06-10
Methods and structures for promoting stable synthesis of carbon nanotubes Grant 7,374,793 - Furukawa , et al. May 20, 2	2008-05-20
Methods Of Fabricating Vertical Carbon Nanotube Field Effect Transistors For Arrangement In Arrays And Field Effect Transistors And Arrays Formed Thereby App 20080044954 - Furukawa; Toshiharu ; et al.	2008-02-21
Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2 App 20080040696 - Hakey; Mark Charles ; et al.	2008-02-14
Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage Grant 7,329,567 - Furukawa , et al. February 12, 2	2008-02-12
Illumination Light In Immersion Lithography Stepper For Particle Or Bubble Detection App 20070296937 - Furukawa; Toshiharu ; et al.	2007-12-27
SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 App 20070228510 - Hakey; Mark Charles ; et al.	2007-10-04
Shallow trench isolation fill by liquid phase deposition of SiO2 Grant 7,273,794 - Hakey , et al. September 25, 2	2007-09-25
Wrap-around gate field effect transistor Grant 7,271,444 - Furukawa , et al. September 18, 2	2007-09-18
Wafer cell for immersion lithography Grant 7,271,878 - Furukawa , et al. September 18, 2	2007-09-18
Methods of forming alternating phase shift masks having improved phase-shift tolerance Grant 7,264,415 - Furukawa , et al. September 4, 2	2007-09-04
Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes App 20070184647 - Furukawa; Toshiharu ; et al.	2007-08-09
Wrap-around Gate Field Effect Transistor App 20070184588 - Furukawa; Toshiharu ; et al.	2007-08-09
Double-gate FETs (Field Effect Transistors) Grant 7,250,347 - Furukawa , et al. July 31, 2	2007-07-31
Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes Grant 7,229,909 - Furukawa , et al. June 12, 2	2007-06-12
Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage Grant 7,211,844 - Furukawa , et al. May 1, 2	2007-05-01
Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers App 20070048879 - Furukawa; Toshiharu ; et al.	2007-03-01
Immersion Lithography With Equalized Pressure On At Least Projection Optics Component And Wafer App 20060289794 - Furukawa; Toshiharu ; et al.	2006-12-28
Method For Making Integrated Circuit Chip Having Carbon Nanotube Composite Interconnection Vias App 20060292861 - Furukawa; Toshiharu ; et al.	2006-12-28
Integrated circuit chip utilizing carbon nanotube composite interconnection vias Grant 7,135,773 - Furukawa , et al. November 14, 2	2006-11-14
Integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,129,097 - Furukawa , et al. October 31, 2	2006-10-31
Horizontal memory gain cells Grant 7,109,546 - Furukawa , et al. September 19, 2	2006-09-19
Moving lens for immersion optical lithography Grant 7,088,422 - Hakey , et al. August 8, 2	2006-08-08
Vertical Carbon Nanotube Transistor Integration App 20060169972 - Furukawa; Toshiharu ; et al.	2006-08-03
DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS) App 20060172496 - Furukawa; Toshiharu ; et al.	2006-08-03
Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes App 20060128137 - Furukawa; Toshiharu ; et al.	2006-06-15
Selective synthesis of semiconducting carbon nanotubes Grant 7,038,299 - Furukawa , et al. May 2, 2	2006-05-02
Liquid-filled balloons for immersion lithography Grant 7,026,259 - Hakey , et al. April 11, 2	2006-04-11
System and apparatus for photolithography Grant 7,027,125 - Hakey , et al. April 11, 2	2006-04-11
Sub-lithographic Imaging Techniques And Processes App 20060060562 - Furukawa; Toshiharu ; et al.	2006-03-23
Alternating phase mask built by additive film deposition Grant 6,998,204 - Furukawa , et al. February 14, 2	2006-02-14
Integrated circuit chip utilizing oriented carbon nanotube conductive layers App 20060022221 - Furukawa; Toshiharu ; et al.	2006-02-02
Method of forming FinFET gates without long etches Grant 6,989,308 - Furukawa , et al. January 24, 2	2006-01-24
Dual gated finfet gain cell App 20060008927 - Furukawa; Toshiharu ; et al.	2006-01-12
Horizontal memory gain cells App 20050286293 - Furukawa, Toshiharu ; et al.	2005-12-29
Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage App 20050266627 - Furukawa, Toshiharu ; et al.	2005-12-01
Dual gated finfet gain cell Grant 6,970,372 - Furukawa , et al. November 29, 2	2005-11-29
Wafer cell for immersion lithography App 20050237501 - Furukawa, Toshiharu ; et al.	2005-10-27
System and apparatus for photolithography App 20050213061 - Hakey, Mark Charles ; et al.	2005-09-29
Methods of forming alternating phase shift masks having improved phase-shift tolerance App 20050202322 - Furukawa, Toshiharu ; et al.	2005-09-15
Method of forming FinFET gates without long etches App 20050202607 - Furukawa, Toshiharu ; et al.	2005-09-15
Integrated circuit chip utilizing carbon nanotube composite interconnection vias App 20050189655 - Furukawa, Toshiharu ; et al.	2005-09-01
Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby App 20050179029 - Furukawa, Toshiharu ; et al.	2005-08-18
Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage App 20050167740 - Furukawa, Toshiharu ; et al.	2005-08-04
Vertical nanotube semiconductor device structures and methods of forming the same App 20050167655 - Furukawa, Toshiharu ; et al.	2005-08-04
Liquid-filled Balloons For Immersion Lithography App 20050158673 - Hakey, Mark C. ; et al.	2005-07-21
Vertical Carbon Nanotube Field Effect Transistor App 20050145838 - Furukawa, Toshiharu ; et al.	2005-07-07
Moving lens for immersion optical lithography App 20050145803 - Hakey, Mark Charles ; et al.	2005-07-07
Shallow trench isolation fill by liquid phase deposition of SiO2 App 20050130387 - Hakey, Mark Charles ; et al.	2005-06-16
Methods and structures for promoting stable synthesis of carbon nanotubes App 20050129948 - Furukawa, Toshiharu ; et al.	2005-06-16
Wrap-around gate field effect transistor App 20050127466 - Furukawa, Toshiharu ; et al.	2005-06-16
Selective synthesis of semiconducting carbon nanotubes App 20050130341 - Furukawa, Toshiharu ; et al.	2005-06-16
Alternating Phase Mask Built By Additive Film Deposition App 20050106472 - Furukawa, Toshiharu ; et al.	2005-05-19
Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby Grant 6,890,828 - Horak , et al. May 10, 2	2005-05-10
Method Of Forming Gas Dielectric With Support Structure App 20050087875 - Furukawa, Toshiharu ; et al.	2005-04-28
Method for forming quadruple density sidewall image transfer (SIT) structures Grant 6,875,703 - Furukawa , et al. April 5, 2	2005-04-05
Method of forming gas dielectric with support structure Grant 6,875,685 - Furukawa , et al. April 5, 2	2005-04-05
Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby App 20040245637 - Horak, David Vaclav ; et al.	2004-12-09
Method for manufacturing a multi-level interconnect structure Grant 6,713,835 - Horak , et al. March 30, 2	2004-03-30
Dual use alignment aid Grant 6,342,735 - Colelli , et al. January 29, 2	2002-01-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.