loadpatents
name:-0.0087769031524658
name:-0.0048251152038574
name:-0.0086488723754883
MINUTILLO; Nicholas G. Patent Filings

MINUTILLO; Nicholas G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for MINUTILLO; Nicholas G..The latest application filed is for "transistor with isolation below source and drain".

Company Profile
8.4.10
  • MINUTILLO; Nicholas G. - Beaverton OR
  • Minutillo; Nicholas G. - Hillsboro OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Transistor With Isolation Below Source And Drain
App 20220028972 - RACHMADY; Willy ;   et al.
2022-01-27
Transistor with isolation below source and drain
Grant 11,171,207 - Rachmady , et al. November 9, 2
2021-11-09
Channel layer formed in an art trench
Grant 11,164,974 - Rachmady , et al. November 2, 2
2021-11-02
Group III-V semiconductor devices having asymmetric source and drain structures
Grant 11,164,747 - Ma , et al. November 2, 2
2021-11-02
Art trench spacers to enable fin release for non-lattice matched channels
Grant 11,049,773 - Dewey , et al. June 29, 2
2021-06-29
High Aspect Ration Source Or Drain Structures With Abrupt Dopant Profile
App 20210091181 - KEECH; Ryan ;   et al.
2021-03-25
Source Or Drain Structures With Phosphorous And Arsenic Co-dopants
App 20200312958 - MURTHY; Anand ;   et al.
2020-10-01
Transistors With High Density Channel Semiconductor Over Dielectric Material
App 20200287024 - Dewey; Gilbert ;   et al.
2020-09-10
Transistor With Isolation Below Source And Drain
App 20200279916 - Rachmady; Willy ;   et al.
2020-09-03
Improved Channel Layer Formed In An Art Trench
App 20200220017 - Rachmady; Willy ;   et al.
2020-07-09
Group Iii-v Semiconductor Devices Having Asymmetric Source And Drain Structures
App 20200203169 - MA; Sean T. ;   et al.
2020-06-25
Arsenic-doped Epitaxial Source/drain Regions For Nmos
App 20200105754 - Murthy; Anand ;   et al.
2020-04-02
Dielectric Lining Layers For Semiconductor Devices
App 20200006501 - Rachmady; Willy ;   et al.
2020-01-02
Art Trench Spacers To Enable Fin Release For Non-lattice Matched Channels
App 20190267289 - DEWEY; Gilbert ;   et al.
2019-08-29

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