Miner; David E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miner; David E..The latest application filed is for "test access port".

Company Profile

0.41.34

Miner; David E. - Chandler AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for use of a preload instruction to improve efficiency of cache Grant 9,892,051 - Jamil , et al. February 13, 2	2018-02-13
Method and apparatus for associating requests and responses with identification information Grant 9,086,976 - O'Bleness , et al. July 21, 2	2015-07-21
Cache memory bank selection Grant 8,990,505 - Jamil , et al. March 24, 2	2015-03-24
Programmable cache access protocol to optimize power consumption and performance Grant 8,769,204 - Delgross , et al. July 1, 2	2014-07-01
Method and apparatus for associating requests and responses with identification information Grant 8,688,919 - O'Bleness , et al. April 1, 2	2014-04-01
Way-selecting translation lookaside buffer Grant 8,631,206 - O'Bleness , et al. January 14, 2	2014-01-14
Implementing direct access caches in coherent multiprocessors Grant 8,533,401 - Edirisooriya , et al. September 10, 2	2013-09-10
Programmable cache access protocol to optimize power consumption and performance Grant 8,458,404 - Delgross , et al. June 4, 2	2013-06-04
Method and apparatus for data-less bus query Grant 8,296,525 - O'Bleness , et al. October 23, 2	2012-10-23
Method and apparatus for hardware-configurable multi-policy coherence protocol Grant 8,135,916 - O'Bleness , et al. March 13, 2	2012-03-13
Test access port Grant 8,065,576 - Miner , et al. November 22, 2	2011-11-22
Power optimized replay of blocked operations in a pipilined architecture Grant 7,966,477 - Jamil , et al. June 21, 2	2011-06-21
Apparatus and method for arbitrating heterogeneous agents in on-chip busses Grant 7,765,349 - Edirisooriya , et al. July 27, 2	2010-07-27
Method and apparatus for optimizing line writes in cache coherent systems Grant 7,757,046 - Jamil , et al. July 13, 2	2010-07-13
Apparatus and method for power optimized replay via selective recirculation of instructions Grant 7,725,683 - Jamil , et al. May 25, 2	2010-05-25
Cache memory to support a processor's power mode of operation Grant 7,685,379 - Edirisooriya , et al. March 23, 2	2010-03-23
Test Access Port App 20100050019 - Miner; David E. ; et al.	2010-02-25
Method and apparatus for implementing heterogeneous interconnects Grant 7,640,387 - Edirisooriya , et al. December 29, 2	2009-12-29
System and apparatus for early fixed latency subtractive decoding Grant 7,634,603 - Edirisooriya , et al. December 15, 2	2009-12-15
Test access port Grant 7,627,797 - Miner , et al. December 1, 2	2009-12-01
Cache memory to support a processor's power mode of operation Grant 7,487,299 - Edirisooriya , et al. February 3, 2	2009-02-03
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors Grant 7,464,227 - Edirisooriya , et al. December 9, 2	2008-12-09
System and Apparatus for Early Fixed Latency Subtractive Decoding App 20080282008 - Edirisooriya; Samantha J. ; et al.	2008-11-13
Method And Apparatus For Implementing Heterogeneous Interconnects App 20080250168 - Edirisooriya; Samantha J. ; et al.	2008-10-09
Apparatus and method for arbitrating heterogeneous agents in on-chip busses Grant 7,428,607 - Edirisooriya , et al. September 23, 2	2008-09-23
Systems and methods for early fixed latency subtractive decoding including speculative acknowledging Grant 7,406,552 - Edirisooriya , et al. July 29, 2	2008-07-29
System and apparatus for early fixed latency subtractive decoding Grant 7,406,553 - Edirisooriya , et al. July 29, 2	2008-07-29
Cache memory to support a processor's power mode of operation Grant 7,404,043 - Edirisooriya , et al. July 22, 2	2008-07-22
Pushing of clean data to one or more processors in a system having a coherency protocol Grant 7,366,845 - Jamil , et al. April 29, 2	2008-04-29
Method and apparatus for implementing heterogeneous interconnects Grant 7,353,317 - Edirisooriya , et al. April 1, 2	2008-04-01
Cache memory to support a processor's power mode of operation Grant 7,290,093 - Edirisooriya , et al. October 30, 2	2007-10-30
System And Apparatus For Early Fixed Latency Subtractive Decoding App 20070186019 - Edirisooriya; Samantha J. ; et al.	2007-08-09
Method and apparatus for fixed latency subtractive decoding App 20070162672 - Edirisooriya; Samantha J. ; et al.	2007-07-12
Power/performance optimized cache using memory write prevention through write snarfing Grant 7,234,028 - Edirisooriya , et al. June 19, 2	2007-06-19
System and apparatus for early fixed latency subtractive decoding Grant 7,219,176 - Edirisooriya , et al. May 15, 2	2007-05-15
Direct processor cache access within a system having a coherent multi-processor protocol Grant 7,159,077 - Tu , et al. January 2, 2	2007-01-02
Apparatus and method for supporting heterogeneous agents in on-chip busses App 20060271716 - Edirisooriya; Samantha J. ; et al.	2006-11-30
Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies Grant 7,143,220 - Edirisooriya , et al. November 28, 2	2006-11-28
Test access port Grant 7,139,947 - Miner , et al. November 21, 2	2006-11-21
Test access port App 20060248426 - Miner; David E. ; et al.	2006-11-02
Methods and apparatus for cache intervention Grant 7,100,001 - Edirisooriya , et al. August 29, 2	2006-08-29
Method and apparatus for implementing heterogeneous interconnects App 20060143358 - Edirisooriya; Samantha J. ; et al.	2006-06-29
Methods and apparatus for cache intervention Grant 7,062,613 - Jamil , et al. June 13, 2	2006-06-13
Techniques for pushing data to a processor cache App 20060112238 - Jamil; Sujat ; et al.	2006-05-25
Direct processor cache access within a system having a coherent multi-processor protocol App 20060004965 - Tu; Steven J. ; et al.	2006-01-05
Direct processor cache access within a system having a coherent multi-processor protocol App 20060004961 - Tu; Steven J. ; et al.	2006-01-05
Methods and apparatus for cache intervention Grant 6,983,348 - Jamil , et al. January 3, 2	2006-01-03
Pushing of clean data to one or more processors in a system having a coherency protocol App 20050289303 - Jamil, Sujat ; et al.	2005-12-29
Apparatus and method for supporting heterogeneous agents in on-chip busses App 20050216632 - Edirisooriya, Samantha J. ; et al.	2005-09-29
Cache memory to support a processor's power mode of operation App 20050204195 - Edirisooriya, Samantha J. ; et al.	2005-09-15
Cache memory to support a processor's power mode of operation App 20050204202 - Edirisooriya, Samantha J. ; et al.	2005-09-15
Cache memory to support a processor's power mode of operation App 20050193176 - Edirisooriya, Samantha J. ; et al.	2005-09-01
Methods and apparatus for cache intervention App 20050166020 - Jamil, Sujat ; et al.	2005-07-28
Methods and apparatus to dispatch interrupts in multi-processor systems App 20050125582 - Tu, Steven J. ; et al.	2005-06-09
Apparatus and method for power optimized replay App 20050071603 - Jamil, Sujat ; et al.	2005-03-31
Methods and apparatus for transferring cache block ownership Grant 6,775,748 - Jamil , et al. August 10, 2	2004-08-10
Methods and apparatus for detecting an address conflict App 20040153611 - Jamil, Sujat ; et al.	2004-08-05
Cache memory to support a processor's power mode of operation App 20040133746 - Edirisooriya, Samantha J. ; et al.	2004-07-08
Power/performance optimized caches using memory write prevention through write snarfing App 20040128451 - Edirisooriya, Samantha J. ; et al.	2004-07-01
Implementing direct access caches in coherent multiprocessors App 20040128450 - Edirisooriya, Samantha J. ; et al.	2004-07-01
Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors App 20040111563 - Edirisooriya, Samantha J. ; et al.	2004-06-10
Method and apparatus for supporting opportunistic sharing in coherent multiprocessors App 20040111566 - Edirisooriya, Samantha J. ; et al.	2004-06-10
Method and apparatus for fixed latency subtractive decoding App 20040064616 - Edirisooriya, Samantha J. ; et al.	2004-04-01
Method and apparatus for optimizing line writes in cache coherent systems App 20040064643 - Jamil, Sujat ; et al.	2004-04-01
Method, system, and apparatus for an efficient cache to support multiple configurations App 20040015669 - Edirisooriya, Samantha J. ; et al.	2004-01-22
Conditional read and invalidate for use in coherent multiprocessor systems App 20030195939 - Edirisooriya, Samatha J. ; et al.	2003-10-16
Methods and apparatus for cache intervention App 20030154350 - Edirisooriya, Samantha J. ; et al.	2003-08-14
Methods and apparatus for cache intervention App 20030154352 - Jamil, Sujat ; et al.	2003-08-14
Methods and apparatus for transferring cache block ownership App 20030140200 - Jamil, Sujat ; et al.	2003-07-24
Method and apparatus for testing multi-core processors App 20030005380 - Nguyen, Hang T. ; et al.	2003-01-02
Test access port App 20020083387 - Miner, David E. ; et al.	2002-06-27