Miller, Jr.; Robert H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miller, Jr.; Robert H..The latest application filed is for "system and method for internal ac coupling with active dc restore and adjustable high-pass filter for a pam 2/4 receiver".

Company Profile

0.17.1

Miller, Jr.; Robert H. - Loveland CO
Miller, Jr.; Robert H - Loveland CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for internal AC coupling with active DC restore and adjustable high-pass filter for a PAM 2/4 receiver Grant 9,237,045 - Kizer , et al. January 12, 2	2016-01-12
System and Method For Internal AC Coupling With Active DC Restore and Adjustable High-Pass Filter for a PAM 2/4 Receiver App 20140269998 - Kizer; Jade Michael ; et al.	2014-09-18
Random noise generator and a method for generating random noise Grant 7,401,108 - Miller, Jr. July 15, 2	2008-07-15
Self-initializing frequency divider Grant 7,268,597 - Miller, Jr. September 11, 2	2007-09-11
Frequency divider with slip Grant 7,196,558 - Miller, Jr. March 27, 2	2007-03-27
Method and apparatus for asynchronous read control Grant 7,082,504 - Rojas , et al. July 25, 2	2006-07-25
Random bit stream generation by amplification of thermal noise in a CMOS process Grant 7,007,060 - Miller, Jr. February 28, 2	2006-02-28
Method and apparatus for low latency distribution of logic signals Grant 6,703,869 - Miller , et al. March 9, 2	2004-03-09
Transparent data-triggered pipeline latch Grant 5,889,979 - Miller, Jr. , et al. March 30, 1	1999-03-30
Trailing bit anticipator Grant 5,754,458 - Beraha , et al. May 19, 1	1998-05-19
Method and apparatus for at speed observability of pipelined circuits Grant 5,740,181 - Heikes , et al. April 14, 1	1998-04-14
Quiescent current testing of dynamic logic systems Grant 5,557,620 - Miller, Jr. , et al. September 17, 1	1996-09-17
Clocking systems and methods for pipelined self-timed dynamic logic circuits Grant 5,434,520 - Yetter , et al. July 18, 1	1995-07-18
System and method for reducing latency in a floating point processor Grant 5,390,134 - Heikes , et al. February 14, 1	1995-02-14
Self-timed clocking system and method for self-timed dynamic logic circuits Grant 5,329,176 - Miller, Jr. , et al. July 12, 1	1994-07-12
Mitigating the adverse effects of charge sharing in dynamic logic circuits Grant 5,317,204 - Yetter , et al. May 31, 1	1994-05-31
Gradient calculation for texture mapping Grant 5,224,208 - Miller, Jr. , et al. June 29, 1	1993-06-29
High speed low skew clock circuit Grant 5,057,701 - Miller, Jr. October 15, 1	1991-10-15

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