Miller; Joseph P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miller; Joseph P..The latest application filed is for "back drill verification feature".

Company Profile

0.14.7

Miller; Joseph P. - Cypress TX
Miller; Joseph P. - Houston TX
Miller; Joseph P. - Tariffville CT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Back Drill Verification Feature App 20120012380 - Miller; Joseph P.	2012-01-19
Use of operational configuration parameters to predict system failures Grant 7,877,645 - Meyer , et al. January 25, 2	2011-01-25
Use Of Operational Configuration Parameters To Predict System Failures App 20090037777 - MEYER; John E. ; et al.	2009-02-05
Testing a receiver connected to a reference voltage signal Grant 7,299,380 - Miller November 20, 2	2007-11-20
Power control unit that provides one of a plurality of voltages on a common power rail Grant 7,073,078 - Srinivasan , et al. July 4, 2	2006-07-04
Methods for measuring die temperature App 20060063285 - Miller; Joseph P.	2006-03-23
Testing a receiver connected to a reference voltage signal App 20050177771 - Miller, Joseph P.	2005-08-11
Power control unit that provides one of a plurality of voltages on a common power rail App 20050132236 - Srinivasan, Karthigan ; et al.	2005-06-16
Integrated circuit device/circuit board connection apparatus App 20040104466 - Miller, Joseph P. ; et al.	2004-06-03
Integrated circuit device/circuit board connection apparatus Grant 6,717,821 - Miller , et al. April 6, 2	2004-04-06
Integrated circuit device/circuit board connection apparatus App 20030016490 - Miller, Joseph P. ; et al.	2003-01-23
Method and apparatus for identifying faulty devices in a computer system Grant 6,032,271 - Goodrum , et al. February 29, 2	2000-02-29
Data error detection and correction Grant 6,024,486 - Olarig , et al. February 15, 2	2000-02-15
Method and apparatus for diagnosing fault states in a computer system Grant 6,000,040 - Culley , et al. December 7, 1	1999-12-07
Bus ring-back and voltage over-shoot reduction techniques coupled with hot-pluggability Grant 5,938,751 - Tavallaei , et al. August 17, 1	1999-08-17
Synchronizing data between devices Grant 5,822,571 - Goodrum , et al. October 13, 1	1998-10-13
Switching control in a fault tolerant system Grant 5,822,512 - Goodrum , et al. October 13, 1	1998-10-13
Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits Grant 5,406,590 - Miller , et al. April 11, 1	1995-04-11
Coprocessor detection circuit Grant 5,134,713 - Miller , et al. July 28, 1	1992-07-28
Negative feedback circuit to control the duty cycle of a logic system clock Grant 4,959,557 - Miller September 25, 1	1990-09-25
Shut Off System For Glassware Forming Machine Grant 3,867,122 - Miller February 18, 1	1975-02-18

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