Miller; Ian D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miller; Ian D..The latest application filed is for "content-based caching in a managed runtime computing environment".

Company Profile

0.25.0

Miller; Ian D. - Charlotte NC
Miller; Ian D. - Raleigh NC
Miller; Ian D. - Columbia MD

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Content-based caching in a managed runtime computing environment Grant 9,411,744 - Janneck , et al. August 9, 2	2016-08-09
Method of generating data for estimating resource requirements for a circuit design Grant 9,117,046 - Schumacher , et al. August 25, 2	2015-08-25
Automatic queue sizing for dataflow applications Grant 8,595,391 - Miller , et al. November 26, 2	2013-11-26
Method and apparatus for processing an event notification in a concurrent processing system Grant 8,572,432 - Parlour , et al. October 29, 2	2013-10-29
Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit Grant 8,402,164 - Parlour , et al. March 19, 2	2013-03-19
Method of evaluating an architecture for an integrated circuit device Grant 8,146,040 - Janneck , et al. March 27, 2	2012-03-27
Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations Grant 8,020,139 - Neuendorffer , et al. September 13, 2	2011-09-13
Automated method of architecture mapping selection from constrained high level language description via element characterization Grant 8,001,510 - Miller , et al. August 16, 2	2011-08-16
Method of estimating resource requirements for a circuit design Grant 7,979,835 - Schumacher , et al. July 12, 2	2011-07-12
Dataflow control for application with timing parameters Grant 7,822,886 - Miller , et al. October 26, 2	2010-10-26
Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages Grant 7,509,619 - Miller , et al. March 24, 2	2009-03-24
Generation of a hardware interface for a software procedure Grant 7,222,314 - Miller , et al. May 22, 2	2007-05-22
Method of transforming software language constructs to functional hardware equivalents Grant 7,143,388 - Miller , et al. November 28, 2	2006-11-28
Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations Grant 7,111,274 - Edwards , et al. September 19, 2	2006-09-19
Determining hardware generated by high level language compilation through loop optimizations Grant 7,086,047 - Edwards , et al. August 1, 2	2006-08-01
Generating hardware interfaces for designs specified in a high level language Grant 6,952,817 - Harris , et al. October 4, 2	2005-10-04
Method of transforming software language constructs to functional hardware equivalents Grant 6,877,150 - Miller , et al. April 5, 2	2005-04-05
System for transmitting and receiving data within a reliable communications protocol by concurrently processing portions of the protocol suite Grant 6,345,302 - Bennett , et al. February 5, 2	2002-02-05
System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects Grant 6,230,307 - Davis , et al. May 8, 2	2001-05-08
Apparatus and method for constructing data for transmission within a reliable communication protocol by performing portions of the protocol suite concurrently Grant 6,122,670 - Bennett , et al. September 19, 2	2000-09-19

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