Miles; Glen L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Miles; Glen L..The latest application filed is for "arranging through silicon vias in ic layout".

Company Profile

0.11.5

Miles; Glen L. - Hopewell Junction NY
Miles; Glen L. - Essex Junction VT
Miles; Glen L. - South Burlington VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Arranging through silicon vias in IC layout Grant 8,136,084 - Dean, Jr. , et al. March 13, 2	2012-03-13
Arranging Through Silicon Vias In Ic Layout App 20110057319 - Dean, JR.; Donald R. ; et al.	2011-03-10
CMOS transistor with a polysilicon gate electrode having varying grain size Grant 7,714,366 - Ballantine , et al. May 11, 2	2010-05-11
Cmos Transistor With A Polysilicon Gate Electrode Having Varying Grain Size App 20050110096 - Ballantine, Arne W. ; et al.	2005-05-26
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size Grant 6,893,948 - Ballantine , et al. May 17, 2	2005-05-17
Structure and method for formation of a blocked silicide resistor Grant 6,853,032 - Ballantine , et al. February 8, 2	2005-02-08
Structure and method for formation of a blocked silicide resistor App 20040135214 - Ballantine, Arne W. ; et al.	2004-07-15
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size App 20040023476 - Ballantine, Arne W. ; et al.	2004-02-05
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size Grant 6,670,263 - Ballantine , et al. December 30, 2	2003-12-30
Structure and method for formation of a blocked silicide resistor Grant 6,660,664 - Adkisson , et al. December 9, 2	2003-12-09
Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication App 20010009291 - Miles, Glen L.	2001-07-26
Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication Grant 6,235,597 - Miles May 22, 2	2001-05-22
Triple polysilicon embedded NVRAM cell and method thereof Grant 6,180,456 - Lam , et al. January 30, 2	2001-01-30
Damascene NVRAM cell and method of manufacture Grant 6,060,358 - Bracchitta , et al. May 9, 2	2000-05-09
Method for lowering the phase transformation temperature of a metal silicide Grant 5,510,295 - Cabral, Jr. , et al. April 23, 1	1996-04-23
Silicide bridge contact process Grant 4,983,544 - Lu , et al. January 8, 1	1991-01-08

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