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Patent applications and USPTO patent grants for Mielich; Harald.The latest application filed is for "reusable structured hardware description language design component".
Patent | Date |
---|---|
Soft-bounded hierarchical synthesis Grant 8,375,345 - Barowski , et al. February 12, 2 | 2013-02-12 |
Reusable structured hardware description language design component Grant 8,332,787 - Kessler , et al. December 11, 2 | 2012-12-11 |
Reusable Structured Hardware Description Language Design Component App 20120117524 - Kessler; Friedhelm ;   et al. | 2012-05-10 |
Combined logic function for address limit checking Grant 6,836,835 - Haller , et al. December 28, 2 | 2004-12-28 |
Floating point bypass register to resolve data dependencies in pipelined instruction sequences App 20040143613 - Clemen, Rainer ;   et al. | 2004-07-22 |
Combined logic function for address limit checking App 20020199080 - Haller, Wilhelm E. ;   et al. | 2002-12-26 |
High-precision voltage dependent timing delay circuit Grant 5,796,284 - Clemen , et al. August 18, 1 | 1998-08-18 |
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