Patent | Date |
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Content addressable memory (CAM) devices that perform pipelined multi-cycle look-up operations using cam sub-arrays and longest match detection Grant RE40,932 - Diede , et al. October 6, 2 | 2009-10-06 |
Fully synchronous pipelined RAM Grant 6,785,188 - Mick August 31, 2 | 2004-08-31 |
Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same Grant 6,665,202 - Lindahl , et al. December 16, 2 | 2003-12-16 |
Fully synchronous pipelined RAM Grant 6,567,338 - Mick May 20, 2 | 2003-05-20 |
Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same App 20030058671 - Lindahl, Craig A. ;   et al. | 2003-03-27 |
Fully synchronous pipelined RAM App 20020154548 - Mick, John R. | 2002-10-24 |
Pipelining a content addressable memory cell array for low-power operation Grant 6,470,418 - Lien , et al. October 22, 2 | 2002-10-22 |
Content addressable memory with longest match detect Grant 6,370,613 - Diede , et al. April 9, 2 | 2002-04-09 |
Fully synchronous pipelined ram Grant 6,249,480 - Mick June 19, 2 | 2001-06-19 |
Separate byte control on fully synchronous pipelined SRAM Grant 6,115,320 - Mick , et al. September 5, 2 | 2000-09-05 |
Fully synchronous pipelined RAM Grant 6,094,399 - Mick July 25, 2 | 2000-07-25 |
Separate byte control on fully synchronous pipelined SRAM Grant 6,081,478 - Mick , et al. June 27, 2 | 2000-06-27 |
Fully synchronous pipelined ram Grant 5,875,151 - Mick February 23, 1 | 1999-02-23 |
Fully synchronous pipelined ram Grant 5,841,732 - Mick November 24, 1 | 1998-11-24 |
Fully synchronous pipelined ram Grant 5,838,631 - Mick November 17, 1 | 1998-11-17 |
Fully synchronous pipelined RAM Grant 5,828,606 - Mick October 27, 1 | 1998-10-27 |
Diagnostic circuit Grant 5,581,564 - Miller , et al. December 3, 1 | 1996-12-03 |
Expandable digital error detection and correction device Grant 5,331,645 - Miller , et al. July 19, 1 | 1994-07-19 |
Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer Grant 5,175,819 - Le Ngoc , et al. December 29, 1 | 1992-12-29 |
Logical grouping of facilities within a computer development system Grant 4,782,461 - Mick , et al. November 1, 1 | 1988-11-01 |
Thirty-two bit, bit slice processor Grant 4,760,517 - Miller , et al. July 26, 1 | 1988-07-26 |
Emulator for non-fixed instruction set VLSI devices Grant 4,633,417 - Wilburn , et al. December 30, 1 | 1986-12-30 |
Processor unit for microcomputer systems Grant 4,467,444 - Harmon, Jr. , et al. August 21, 1 | 1984-08-21 |
Interruptable microprogram controller for microcomputer systems Grant 4,438,492 - Harmon, Jr. , et al. March 20, 1 | 1984-03-20 |
Asynchronous Data Signal Reception Grant 3,582,789 - Mick June 1, 1 | 1971-06-01 |