| Patent | Date |
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Electronic device and method of biasing
Grant 8,687,417 - Li , et al. April 1, 2 | 2014-04-01 |
Compensating for layout dimension effects in semiconductor device modeling
Grant 7,793,240 - Sultan , et al. September 7, 2 | 2010-09-07 |
Methods of forming contact openings
Grant 7,670,938 - Wu , et al. March 2, 2 | 2010-03-02 |
Electronic Device And Method Of Biasing
App 20090090969 - Li; Ruigang ; et al. | 2009-04-09 |
Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same
Grant 7,504,270 - Wu , et al. March 17, 2 | 2009-03-17 |
Providing stress uniformity in a semiconductor device
Grant 7,473,623 - Chen , et al. January 6, 2 | 2009-01-06 |
Contact resistance test structure and methods of using same
Grant 7,391,226 - Michael , et al. June 24, 2 | 2008-06-24 |
Compensating For Layout Dimension Effects In Semiconductor Device Modeling
App 20080104550 - Sultan; Akif ; et al. | 2008-05-01 |
Test structure for measuring electrical and dimensional characteristics
Grant 7,355,201 - Zhu , et al. April 8, 2 | 2008-04-08 |
Providing Stress Uniformity In A Semiconductor Device
App 20080003789 - Chen; Jian ; et al. | 2008-01-03 |
Methods Of Quantifying Variations Resulting From Manufacturing-induced Corner Rounding Of Various Features, And Structures For Testing Same
App 20070298524 - WU; DAVID D. ; et al. | 2007-12-27 |
Test Structure For Measuring Electrical And Dimensional Characteristics
App 20070296444 - Zhu; Jianhong ; et al. | 2007-12-27 |
Contact Resistance Test Structure And Methods Of Using Same
App 20070279064 - Michael; Mark W. ; et al. | 2007-12-06 |
Methods Of Forming Contact Openings
App 20070259513 - Wu; David D. ; et al. | 2007-11-08 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance
Grant 6,964,875 - En , et al. November 15, 2 | 2005-11-15 |
Enhanced silicidation of polysilicon gate electrodes
Grant 6,867,130 - Karlsson , et al. March 15, 2 | 2005-03-15 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance
Grant 6,841,832 - En , et al. January 11, 2 | 2005-01-11 |
Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer
Grant 6,780,776 - Qi , et al. August 24, 2 | 2004-08-24 |
SOI device with different silicon thicknesses
Grant 6,764,917 - Chan , et al. July 20, 2 | 2004-07-20 |
Method to reduce parasitic capacitance of MOS transistors
Grant 6,713,357 - Wang , et al. March 30, 2 | 2004-03-30 |
Tri-level segmented control transistor and fabrication method
Grant 6,661,057 - Dawson , et al. December 9, 2 | 2003-12-09 |
Photolithographic system including light filter that compensates for lens error
Grant 6,552,776 - Wristers , et al. April 22, 2 | 2003-04-22 |
Dopant diffusion-retarding barrier region formed within polysilicon gate layer
Grant 6,380,055 - Gardner , et al. April 30, 2 | 2002-04-30 |
Dielectric having an air gap formed between closely spaced interconnect lines
Grant 6,376,330 - Fulford, Jr. , et al. April 23, 2 | 2002-04-23 |
Dopant Diffusion-retarding Barrier Region Formed Within Polysilicon Gate Layer
App 20020004294 - GARDNER, MARK I. ; et al. | 2002-01-10 |
Igfet With Silicide Contact On Ultra-thin Gate
App 20020003273 - DAWSON, ROBERT ; et al. | 2002-01-10 |
Method Of Making An Igfet Using Solid Phase Diffusion To Dope The Gate, Source And Drain
App 20010039094 - WRISTERS, DERICK J. ; et al. | 2001-11-08 |
Semiconductor Isolation Region Bounded By A Trench And Covered With An Oxide To Improve Planarization
App 20010020727 - HAUSE, FRED N. ; et al. | 2001-09-13 |
Multiple split gate semiconductor device and fabrication method
Grant 6,259,142 - Dawson , et al. July 10, 2 | 2001-07-10 |
Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion
Grant 6,225,151 - Gardner , et al. May 1, 2 | 2001-05-01 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 6,208,015 - Bandyopadhyay , et al. March 27, 2 | 2001-03-27 |
Trench transistor with insulative spacers
Grant 6,201,278 - Gardner , et al. March 13, 2 | 2001-03-13 |
Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls
Grant 6,197,645 - Michael , et al. March 6, 2 | 2001-03-06 |
Method of forming an insulated-gate field-effect transistor with metal spacers
Grant 6,188,114 - Gardner , et al. February 13, 2 | 2001-02-13 |
Integrated circuit having interconnect lines separated by a dielectric having a capping layer
Grant 6,153,833 - Dawson , et al. November 28, 2 | 2000-11-28 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 6,150,721 - Bandyopadhyay , et al. November 21, 2 | 2000-11-21 |
Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance
Grant 6,146,978 - Michael , et al. November 14, 2 | 2000-11-14 |
Integrated circuit having conductors of enhanced cross-sectional area
Grant 6,127,264 - Bandyopadhyay , et al. October 3, 2 | 2000-10-03 |
Method of forming trench transistor with insulative spacers
Grant 6,100,146 - Gardner , et al. August 8, 2 | 2000-08-08 |
Fabrication of a non-ldd graded p-channel mosfet
Grant 6,096,616 - Nistler , et al. August 1, 2 | 2000-08-01 |
Dissolvable dielectric method and structure
Grant 6,091,149 - Hause , et al. July 18, 2 | 2000-07-18 |
Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls
Grant 6,087,706 - Dawson , et al. July 11, 2 | 2000-07-11 |
Method and structure for isolating semiconductor devices after transistor formation
Grant 6,074,904 - Spikes, Jr. , et al. June 13, 2 | 2000-06-13 |
Method of making NMOS and PMOS devices with reduced masking steps
Grant 6,060,345 - Hause , et al. May 9, 2 | 2000-05-09 |
Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device
Grant 6,030,752 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines
Grant 6,031,289 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Semiconductor substrate having extended scribe line test structure and method of fabrication thereof
Grant 6,027,859 - Dawson , et al. February 22, 2 | 2000-02-22 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,998,293 - Dawson , et al. December 7, 1 | 1999-12-07 |
Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device
Grant 5,976,956 - Gardner , et al. November 2, 1 | 1999-11-02 |
Method of planarizing a semiconductor topography using multiple polish pads
Grant 5,968,843 - Dawson , et al. October 19, 1 | 1999-10-19 |
Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths
Grant 5,963,803 - Dawson , et al. October 5, 1 | 1999-10-05 |
Dissolvable dielectric method
Grant 5,953,626 - Hause , et al. September 14, 1 | 1999-09-14 |
Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls
Grant 5,937,299 - Michael , et al. August 10, 1 | 1999-08-10 |
Method of making an IGFET with a multilevel gate
Grant 5,930,634 - Hause , et al. July 27, 1 | 1999-07-27 |
Transistor with buried insulative layer beneath the channel region
Grant 5,930,642 - Moore , et al. July 27, 1 | 1999-07-27 |
Method for achieving global planarization by forming minimum mesas in large field areas
Grant 5,926,713 - Hause , et al. July 20, 1 | 1999-07-20 |
Method of making an integrated circuit with oxidizable trench liner
Grant 5,926,717 - Michael , et al. July 20, 1 | 1999-07-20 |
Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size
Grant 5,918,126 - Fulford, Jr. , et al. June 29, 1 | 1999-06-29 |
Method of channel doping using diffusion from implanted polysilicon
Grant 5,918,129 - Fulford, Jr. , et al. June 29, 1 | 1999-06-29 |
Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device
Grant 5,899,732 - Gardner , et al. May 4, 1 | 1999-05-04 |
Method of making an igfet with selectively doped multilevel polysilicon gate
Grant 5,885,887 - Hause , et al. March 23, 1 | 1999-03-23 |
Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric
Grant 5,885,877 - Gardner , et al. March 23, 1 | 1999-03-23 |
Method of forming an insulated-gate field-effect transistor with metal spacers
Grant 5,877,058 - Gardner , et al. March 2, 1 | 1999-03-02 |
Method of reducing overlap between gate electrode and LDD region
Grant 5,869,378 - Michael February 9, 1 | 1999-02-09 |
Integrated circuit having horizontally and vertically offset interconnect lines
Grant 5,854,131 - Dawson , et al. December 29, 1 | 1998-12-29 |
IGFET method of forming with silicide contact on ultra-thin gate
Grant 5,851,891 - Dawson , et al. December 22, 1 | 1998-12-22 |
Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process
Grant 5,851,913 - Brennan , et al. December 22, 1 | 1998-12-22 |
Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric
Grant 5,851,889 - Michael , et al. December 22, 1 | 1998-12-22 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish
Grant 5,850,105 - Dawson , et al. December 15, 1 | 1998-12-15 |
Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
Grant 5,847,462 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 5,846,876 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Individually controllable radiation sources for providing an image pattern in a photolithographic system
Grant 5,840,451 - Moore , et al. November 24, 1 | 1998-11-24 |
Method of making NMOS and devices with sequentially formed gates having different gate lengths
Grant 5,827,761 - Fulford, Jr. , et al. October 27, 1 | 1998-10-27 |
Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines
Grant 5,827,776 - Bandyopadhyay , et al. October 27, 1 | 1998-10-27 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 5,814,555 - Bandyopadhyay , et al. September 29, 1 | 1998-09-29 |
Method of forming trench transistor with metal spacers
Grant 5,801,075 - Gardner , et al. September 1, 1 | 1998-09-01 |
Interlevel dielectric with air gaps to reduce permitivity
Grant 5,792,706 - Michael , et al. August 11, 1 | 1998-08-11 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,783,864 - Dawson , et al. July 21, 1 | 1998-07-21 |
Semiconductor interlevel dielectric having a polymide for producing air gaps
Grant 5,783,481 - Brennan , et al. July 21, 1 | 1998-07-21 |
Method of forming a recessed interconnect structure
Grant 5,767,012 - Fulford, Jr. , et al. June 16, 1 | 1998-06-16 |
Method of formation of an air gap within a semiconductor dielectric by solvent desorption
Grant 5,759,913 - Fulford, Jr. , et al. June 2, 1 | 1998-06-02 |
Inspection of lens error associated with lens heating in a photolithographic system
Grant 5,723,238 - Moore , et al. March 3, 1 | 1998-03-03 |
Method of forming a shallow junction by diffusion from a silicon-based spacer
Grant 5,710,054 - Gardner , et al. January 20, 1 | 1998-01-20 |
Integrated verticle NPN and vertical oxide fuse programmable memory cell
Grant 4,701,780 - Hankins , et al. October 20, 1 | 1987-10-20 |
Method of making an intergrated vertical NPN and vertical oxide fuse programmable memory cell
Grant 4,635,345 - Hankins , et al. January 13, 1 | 1987-01-13 |
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