Meyer; Moritz Andreas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Meyer; Moritz Andreas.The latest application filed is for "metal line layout based on line shifting".

Company Profile

0.11.10

Meyer; Moritz Andreas - Dresden DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Metal line layout based on line shifting Grant 9,898,572 - Melde , et al. February 20, 2	2018-02-20
Metal Line Layout Based On Line Shifting App 20170235867 - Melde; Thomas ; et al.	2017-08-17
Method comprising applying an external mechanical stress to a semiconductor structure and semiconductor processing tool Grant 9,281,252 - Wurfel , et al. March 8, 2	2016-03-08
Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance Grant 8,575,029 - Meyer , et al. November 5, 2	2013-11-05
Method of forming an alloy in an interconnect structure to increase electromigration resistance Grant 8,329,577 - Lehr , et al. December 11, 2	2012-12-11
Technique For Forming Metal Lines In A Semiconductor By Adapting The Temperature Dependence Of The Line Resistance App 20120088365 - Meyer; Moritz Andreas ; et al.	2012-04-12
Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance Grant 8,058,731 - Meyer , et al. November 15, 2	2011-11-15
Method of testing an integrity of a material layer in a semiconductor structure Grant 8,058,081 - Meyer , et al. November 15, 2	2011-11-15
Technique for forming embedded metal lines having increased resistance against stress-induced material transport Grant 8,039,395 - Meyer , et al. October 18, 2	2011-10-18
Increasing Electromigration Resistance in an Interconnect Structure of a Semiconductor Device by Forming an Alloy App 20110124189 - Lehr; Matthias ; et al.	2011-05-26
System and method for estimating the crystallinity of stacked metal lines in microstructures Grant 7,718,447 - Zienert , et al. May 18, 2	2010-05-18
Increasing Electromigration Resistance In An Interconnect Structure Of A Semiconductor Device By Forming An Alloy App 20090197408 - Lehr; Matthias ; et al.	2009-08-06
Technique For Forming Metal Lines In A Semiconductor By Adapting The Temperature Dependence Of The Line Resistance App 20080268265 - Meyer; Moritz Andreas ; et al.	2008-10-30
Method Of Testing An Integrity Of A Material Layer In A Semiconductor Structure App 20080160654 - Meyer; Moritz Andreas ; et al.	2008-07-03
Technique for CD measurement on the basis of area fraction determination Grant 7,335,880 - Langer , et al. February 26, 2	2008-02-26
System And Method For Estimating The Crystallinity Of Stacked Metal Lines In Microstructures App 20070201615 - Zienert; Inka ; et al.	2007-08-30
Technique for CD measurement on the basis of area fraction determination App 20060219906 - Langer; Eckhard ; et al.	2006-10-05
Technique for monitoring the state of metal lines in microstructures Grant 6,953,755 - Meyer , et al. October 11, 2	2005-10-11
Technique for forming embedded metal lines having increased resistance against stress-induced material transport App 20050161817 - Meyer, Moritz-Andreas ; et al.	2005-07-28
Technique for monitoring the state of metal lines in microstructures App 20050072919 - Meyer, Moritz Andreas ; et al.	2005-04-07

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