Merchant; Sailesh M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Merchant; Sailesh M..The latest application filed is for "stacked interconnect heat sink".

Company Profile

0.42.28

Merchant; Sailesh M. - Macungie PA
Merchant; Sailesh M - Macungie PA
Merchant; Sailesh M. - Orlando FL
Merchant; Sailesh M. - Bethlehem Northampton County

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integration of shallow trench isolation and through-substrate vias into integrated circuit designs Grant 9,613,847 - Bachman , et al. April 4, 2	2017-04-04
Stacked Interconnect Heat Sink App 20150214130 - Bachman; Mark A. ; et al.	2015-07-30
Stacked interconnect heat sink Grant 9,054,064 - Bachman , et al. June 9, 2	2015-06-09
Method of fabrication of through-substrate vias Grant 8,987,137 - Bachman , et al. March 24, 2	2015-03-24
Preventing electronic device counterfeits Grant 8,854,115 - Merchant , et al. October 7, 2	2014-10-07
Preventing Electronic Device Counterfeits App 20140253222 - Merchant; Sailesh M. ; et al.	2014-09-11
Integration Of Shallow Trench Isolation And Through-substrate Vias Into Integrated Circuit Designs App 20140220760 - Bachman; Mark A. ; et al.	2014-08-07
Integration of shallow trench isolation and through-substrate vias into integrated circuit designs Grant 8,742,535 - Bachman , et al. June 3, 2	2014-06-03
Contact Support Pillar Structure For Flip Chip Semiconductor Devices And Method Of Manufacture Therefore App 20140015127 - Bachman; Mark A. ; et al.	2014-01-16
Stacked Interconnect Heat Sink App 20130280864 - Bachman; Mark A. ; et al.	2013-10-24
Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore Grant 8,507,317 - Bachman , et al. August 13, 2	2013-08-13
Stacked interconnect heat sink Grant 8,492,911 - Bachman , et al. July 23, 2	2013-07-23
System And Method For Automatically Controlling A Video Presentation App 20130155207 - Freund; Joseph M. ; et al.	2013-06-20
Routing under bond pad for the replacement of an interconnect layer Grant 8,319,343 - Archer, III , et al. November 27, 2	2012-11-27
Method Of Fabrication Of Through-substrate Vias App 20120153492 - Bachman; Mark A. ; et al.	2012-06-21
Integration Of Shallow Trench Isolation And Through-substrate Vias Into Integrated Circuit Designs App 20120153430 - Bachman; Mark A. ; et al.	2012-06-21
Stacked Interconnect Heat Sink App 20120020028 - Bachman; Mark A. ; et al.	2012-01-26
Solder Bump Structure For Flip Chip Semiconductor Devices And Method Of Manufacture Therefor App 20110195544 - Bachman; Mark A. ; et al.	2011-08-11
Thermal monitoring and management of integrated circuits Grant 7,973,544 - Archer, III , et al. July 5, 2	2011-07-05
Solder bump structure for flip chip semiconductor devices and method of manufacture therefore Grant 7,952,206 - Bachman , et al. May 31, 2	2011-05-31
Semiconductor test device with heating circuit Grant 7,804,291 - Kang , et al. September 28, 2	2010-09-28
Thermal Monitoring And Management Of Integrated Circuits App 20100045326 - Archer, III; Vance D. ; et al.	2010-02-25
Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink Grant 7,429,502 - Archer, III , et al. September 30, 2	2008-09-30
Semiconductor with damage detection circuitry Grant 7,397,103 - Archer , et al. July 8, 2	2008-07-08
Test semiconductor device and method for determining Joule heating effects in such a device Grant 7,388,395 - Kang , et al. June 17, 2	2008-06-17
Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink Grant 7,327,029 - Archer, III , et al. February 5, 2	2008-02-05
Integrated Circuit Device Incorporating Metallurgical Bond to Enhance Thermal Conduction to a Heat Sink App 20080026508 - Archer; Vance D. III ; et al.	2008-01-31
Reinforced bond pad for a semiconductor device Grant 7,301,231 - Antol , et al. November 27, 2	2007-11-27
Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process Grant 7,221,173 - Bachman , et al. May 22, 2	2007-05-22
Semiconductor with damage detection circuitry App 20070069365 - Archer; Vance D. ; et al.	2007-03-29
Integrated circuit device incorporating metallurigacal bond to enhance thermal conduction to a heat sink App 20070069368 - Archer; Vance D. III ; et al.	2007-03-29
Solder Bump Structure For Flip Chip Semiconductor Devices And Method Of Manufacture Therefore App 20070069394 - Bachman; Mark A. ; et al.	2007-03-29
Routing Under Bond Pad For The Replacement Of An Interconnect Layer App 20070063352 - Archer; Vance D. III ; et al.	2007-03-22
Reinforced bond pad for a semiconductor device App 20060226535 - Antol; Joze E. ; et al.	2006-10-12
Reinforced bond pad for a semiconductor device Grant 7,115,985 - Antol , et al. October 3, 2	2006-10-03
Test semiconductor device and method for determining Joule heating effects in such a device App 20060192584 - Kang; Seung H. ; et al.	2006-08-31
Test semiconductor device and method for determining Joule heating effects in such a device Grant 7,061,264 - Kang , et al. June 13, 2	2006-06-13
Test semiconductor device and method for determining Joule heating effects in such a device App 20060066337 - Kang; Seung H. ; et al.	2006-03-30
Reinforced bond pad for a semiconductor device App 20060065969 - Antol; Joze E. ; et al.	2006-03-30
Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process App 20060066327 - Bachman; Mark Adam ; et al.	2006-03-30
Method to avoid copper contamination of a via or dual damascene structure Grant 7,005,375 - Karthikeyan , et al. February 28, 2	2006-02-28
Method of fabricating a contact with a post contact plug anneal Grant 6,982,226 - Merchant , et al. January 3, 2	2006-01-03
Junction capacitor structure and fabrication method therefor in a dual damascene process Grant 6,784,478 - Merchant , et al. August 31, 2	2004-08-31
Method of eliminating agglomerate particles in a polishing slurry Grant 6,750,145 - Crevasse , et al. June 15, 2	2004-06-15
Method to avoid copper contamination of a via or dual damascene structure App 20040063307 - Karthikeyan, Subramanian ; et al.	2004-04-01
Capacitor structure and fabrication method therefor in a dual damascene process App 20040061177 - Merchant, Sailesh M. ; et al.	2004-04-01
Microelectronic device layer deposited with multiple electrolytes Grant 6,703,712 - Gilkes , et al. March 9, 2	2004-03-09
Method of coil preparation for ionized metal plasma process and method of manufacturing integrated circuits Grant 6,699,372 - Bhowmik , et al. March 2, 2	2004-03-02
Microelectronic device layer deposited with multiple electrolytes App 20030089986 - Gilkes, Daniele ; et al.	2003-05-15
Curvilinear chemical mechanical planarization device and method Grant 6,537,135 - Easter , et al. March 25, 2	2003-03-25
Method of coil preparation for ionized metal plasma process and method of manufacturing integrated circuits App 20020189932 - Bhowmik, Siddhartha ; et al.	2002-12-19
Method of eliminating agglomerate particles in a polishing slurry App 20020052115 - Crevasse, Annette M. ; et al.	2002-05-02
Multi-layered metal silicide resistor for Si Ic's Grant 6,359,339 - Gregor , et al. March 19, 2	2002-03-19
Method of forming metal oxide metal capacitors using multi-step rapid material thermal process and a device formed thereby App 20020017670 - Bhowmik, Siddhartha ; et al.	2002-02-14
Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same Grant 6,340,827 - Choi , et al. January 22, 2	2002-01-22
Metal silicide as a barrier for MOM capacitors in CMOS technologies Grant 6,335,557 - Kizilyalli , et al. January 1, 2	2002-01-01
DRAM capacitor including Cu plug and Ta barrier and method of forming Grant 6,168,991 - Choi , et al. January 2, 2	2001-01-02
Semiconductor device having aluminum contacts or vias and method of manufacture therefor Grant 6,157,082 - Merchant , et al. December 5, 2	2000-12-05
Method of making a semiconductor with copper passivating film Grant 6,114,234 - Merchant , et al. September 5, 2	2000-09-05
Method of passivating copper interconnects in a semiconductor Grant 6,071,808 - Merchant , et al. June 6, 2	2000-06-06
Semiconductor device having aluminum contacts or vias and method of manufacture therefor Grant 5,913,146 - Merchant , et al. June 15, 1	1999-06-15
Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof Grant 5,858,873 - Vitkavage , et al. January 12, 1	1999-01-12
Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer Grant 5,523,259 - Merchant , et al. June 4, 1	1996-06-04
Multiple layer tungsten deposition process Grant 5,489,552 - Merchant , et al. February 6, 1	1996-02-06
Method of forming silicide in integrated circuit manufacture Grant 5,461,005 - Manocha , et al. October 24, 1	1995-10-24

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