Mercer; Douglas E

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mercer; Douglas E.The latest application filed is for "gate structure and method".

Company Profile

0.9.10

Mercer; Douglas E - Richardson TX
Mercer; Douglas E. - Richardson TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Gate structure and method Grant 8,021,990 - Rotondaro , et al. September 20, 2	2011-09-20
Metal-germanium physical vapor deposition for semiconductor device defect reduction Grant 7,803,703 - Yue , et al. September 28, 2	2010-09-28
Gate Structure And Method App 20090227117 - Rotondaro; Antonio L.P. ; et al.	2009-09-10
Gate structure and method Grant 7,535,066 - Rotondaro , et al. May 19, 2	2009-05-19
Metal-germanium Physical Vapor Deposition For Semiconductor Device Defect Reduction App 20080311747 - Yue; Doufeng ; et al.	2008-12-18
Gate dielectric and method Grant 7,449,385 - Rotondaro , et al. November 11, 2	2008-11-11
Metal-germanium physical vapor deposition for semiconductor device defect reduction Grant 7,435,672 - Yue , et al. October 14, 2	2008-10-14
Metal-halogen physical vapor deposition for semiconductor device defect reduction Grant 7,208,398 - Chen , et al. April 24, 2	2007-04-24
Method for integrating high-k dielectrics in transistor devices Grant 7,045,431 - Rotondaro , et al. May 16, 2	2006-05-16
Metal-germanium physical vapor deposition for semiconductor device defect reduction App 20060024963 - Yue; Doufeng ; et al.	2006-02-02
Metal-halogen physical vapor deposition for semiconductor device defect reduction App 20050208762 - Chen, Peijun J. ; et al.	2005-09-22
Method for integrating high-k dielectrics in transistor devices App 20050136589 - Rotondaro, Antonio L.P. ; et al.	2005-06-23
Memory cell with transistors having relatively high threshold voltages in response to selective gate doping Grant 6,773,972 - Marshall , et al. August 10, 2	2004-08-10
Methods for forming interfacial layer for deposition of high-k dielectrics App 20040126944 - Pacheco Rotondaro, Antonio Luis ; et al.	2004-07-01
Gate dielectric and method App 20040016973 - Rotondaro, Antonio L.P. ; et al.	2004-01-29
Gate structure and method App 20030164525 - Rotondaro, Antonio L. P. ; et al.	2003-09-04
Multi-thickness oxide growth with in-situ scanned laser heating App 20020098712 - Mavoori, Jaideep ; et al.	2002-07-25
Memory cell with transistors having relatively high threshold voltages in response to selective gate doping App 20020084493 - Marshall, Andrew ; et al.	2002-07-04
Rapid thermal annealing of doped polycrystalline silicon structures formed in a single-wafer cluster tool Grant 6,204,198 - Banerjee , et al. March 20, 2	2001-03-20

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