loadpatents
name:-0.03442120552063
name:-0.040239095687866
name:-0.00093984603881836
Memis; Irving Patent Filings

Memis; Irving

Patent Applications and Registrations

Patent applications and USPTO patent grants for Memis; Irving.The latest application filed is for "multi-layer embedded capacitance and resistance substrate core".

Company Profile
0.30.21
  • Memis; Irving - Vestal NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Multi-layer embedded capacitance and resistance substrate core
Grant 8,144,480 - Das , et al. March 27, 2
2012-03-27
High performance chip carrier substrate
Grant 7,886,435 - Audet , et al. February 15, 2
2011-02-15
High performance chip carrier substrate
Grant 7,863,526 - Audet , et al. January 4, 2
2011-01-04
Multi-layer embedded capacitance and resistance substrate core
Grant 7,791,897 - Das , et al. September 7, 2
2010-09-07
Multi-layer Embedded Capacitance And Resistance Substrate Core
App 20100167210 - Das; Rabindra N. ;   et al.
2010-07-01
Mulit-layer embedded capacitance and resistance substrate core
App 20100060381 - Das; Rabindra N. ;   et al.
2010-03-11
Method of making multi-chip electronic package with reduced line skew
Grant 7,622,384 - Memis November 24, 2
2009-11-24
Method of making circuitized substrate with improved impedance control circuitry, electrical assembly and information handling system
Grant 7,589,283 - Danoski , et al. September 15, 2
2009-09-15
Low moisture absorptive circuitized substrate with reduced thermal expansion, method of making same, electrical assembly utilizing same, and information handling system utilizing same
Grant 7,470,990 - Japp , et al. December 30, 2
2008-12-30
High Performance Chip Carrier Substrate
App 20080308923 - Audet; Jean ;   et al.
2008-12-18
High Performance Chip Carrier Substrate
App 20080296054 - Audet; Jean ;   et al.
2008-12-04
High performance chip carrier substrate
Grant 7,454,833 - Audet , et al. November 25, 2
2008-11-25
Method of making same low moisture absorptive circuitized substrave with reduced thermal expansion
Grant 7,416,972 - Japp , et al. August 26, 2
2008-08-26
Method of making multi-chip electronic package with reduced line skew
App 20080102562 - Memis; Irving
2008-05-01
Multi-chip electronic package with reduced line skew and circuitized substrate for use therein
Grant 7,332,818 - Memis February 19, 2
2008-02-19
Method of making circuitized substrate with improved impedance control circuitry, electrical assembly and information handling system
App 20070284140 - Danoski; Charles E. ;   et al.
2007-12-13
Circuitized substrate with improved impedance control circuitry, method of making same, electrical assembly and information handling system utilizing same
Grant 7,294,791 - Danoski , et al. November 13, 2
2007-11-13
High wireability microvia substrate
Grant 7,279,798 - Memis October 9, 2
2007-10-09
Method of making same low moisture absorptive circuitized substrave with reduced thermal expansion
App 20070182016 - Japp; Robert M. ;   et al.
2007-08-09
High performance chip carrier substrate
App 20070175658 - Audet; Jean ;   et al.
2007-08-02
High performance chip carrier substrate
Grant 7,214,886 - Audet , et al. May 8, 2
2007-05-08
Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same
Grant 7,145,221 - Memis , et al. December 5, 2
2006-12-05
Multi-chip electronic package with reduced line skew, method of making same and information handling system utilizing same
App 20060255460 - Memis; Irving
2006-11-16
Extension of fatigue life for C4 solder ball to chip connection
Grant 7,119,003 - Bernier , et al. October 10, 2
2006-10-10
Extension of fatigue life for C4 solder ball to chip connection
Grant 7,067,916 - Bernier , et al. June 27, 2
2006-06-27
Circuitized substrate with improved impedance contol circuitry, method of making same, electrical assembly and information handling system utilizing same
App 20060065433 - Danoski; Charles E. ;   et al.
2006-03-30
High wireability microvia substrate
App 20060012054 - Memis; Irving
2006-01-19
High wireability microvia substrate
Grant 6,965,170 - Memis November 15, 2
2005-11-15
Extension of fatigue life for C4 solder ball to chip connection
App 20050224973 - Bernier, William E. ;   et al.
2005-10-13
Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same
App 20050224251 - Memis, Irving ;   et al.
2005-10-13
Low moisture absorptive circuitized substrate with reduced thermal expansion, method of making same, electrical assembly utilizing same, and information handling system utilizing same
App 20050218524 - Japp, Robert M. ;   et al.
2005-10-06
High density microvia substrate with high wireability
Grant 6,919,635 - Kawasaki , et al. July 19, 2
2005-07-19
High performance chip carrier substrate
App 20050109535 - Audet, Jean ;   et al.
2005-05-26
High wireability microvia substrate
App 20050104221 - Memis, Irving
2005-05-19
High Density Microvia Substrate With High Wireability
App 20050093133 - Kawasaki, Kazushige ;   et al.
2005-05-05
Full additive process with filled plated through holes
Grant 6,664,485 - Bhatt , et al. December 16, 2
2003-12-16
Selective C4 connection in IC packaging
Grant 6,650,016 - MacQuarrie , et al. November 18, 2
2003-11-18
Extension of fatigue life for C4 solder ball to chip connection
App 20020195707 - Bernier, William E. ;   et al.
2002-12-26
Process for manufacturing a multi-layer circuit board
App 20010042733 - Appelt, Bernd K. ;   et al.
2001-11-22
Full additive process with filled plated through holes
App 20010009066 - Bhatt, Anilkumar C. ;   et al.
2001-07-26
Full additive process with filled plated through holes
App 20010007289 - Bhatt, Anilkumar C. ;   et al.
2001-07-12
Attaching heat sinks directly to flip chips and ceramic chip carriers
Grant 6,251,707 - Bernier , et al. June 26, 2
2001-06-26
Full additive process with filled plated through holes
Grant 6,195,883 - Bhatt , et al. March 6, 2
2001-03-06
Circuit board with primary and secondary through holes
Grant 6,162,997 - Memis December 19, 2
2000-12-19
Attaching heat sinks directly to flip chips and ceramic chip carriers
Grant 6,069,023 - Bernier , et al. May 30, 2
2000-05-30
Printed circuit boards for mounting a semiconductor integrated circuit die
Grant 5,965,944 - Frankoski , et al. October 12, 1
1999-10-12
Attaching heat sinks directly to flip chips and ceramic chip carriers
Grant 5,847,929 - Bernier , et al. December 8, 1
1998-12-08
Method of making an electronic package assembly with protective encapsulant material
Grant 5,414,928 - Bonitz , et al. May 16, 1
1995-05-16
Electrical and/or thermal interconnections and methods for obtaining such
Grant 5,189,261 - Alexander , et al. February 23, 1
1993-02-23
Method and structure for preventing wet etchant penetration at the interface between a resist mask and an underlying metal layer
Grant 4,971,894 - Memis , et al. November 20, 1
1990-11-20
Hermetic topsealant coating and process for its formation
Grant 4,048,356 - Bakos , et al. September 13, 1
1977-09-13

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