Melo; Maria L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Melo; Maria L..The latest application filed is for "system and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations".

Company Profile

0.17.0

Melo; Maria L. - Houston TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations Grant 6,279,087 - Melo , et al. August 21, 2	2001-08-21
Device and method for dynamically reducing power consumption within input buffers of a bus interface unit Grant 6,243,817 - Melo , et al. June 5, 2	2001-06-05
Configuration logic within a PCI compliant bus interface unit which can be selectively disconnected from a clocking source to conserve power Grant 6,241,400 - Melo , et al. June 5, 2	2001-06-05
Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base Grant 6,212,590 - Melo , et al. April 3, 2	2001-04-03
Computer system employing optimized delayed transaction arbitration technique Grant 6,199,131 - Melo , et al. March 6, 2	2001-03-06
Device and method for reducing power consumption within an accelerated graphics port target Grant 6,040,845 - Melo , et al. March 21, 2	2000-03-21
Computer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions Grant 5,991,833 - Wandler , et al. November 23, 1	1999-11-23
Dynamic delayed transaction discard counter in a bus bridge of a computer system Grant 5,987,555 - Alzien , et al. November 16, 1	1999-11-16
Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus Grant 5,923,859 - Melo , et al. July 13, 1	1999-07-13
PCI to PCI bridge for transparently completing transactions between agents on opposite sides of the bridge Grant 5,918,026 - Melo , et al. June 29, 1	1999-06-29
Preventing corruption in a multiple processor computer system during a peripheral device configuration cycle Grant 5,867,728 - Melo , et al. February 2, 1	1999-02-02
Bus master arbitration circuitry having improved prioritization Grant 5,797,020 - Bonella , et al. August 18, 1	1998-08-18
Circuit for selectively preventing a microprocessor from posting write cycles Grant 5,625,824 - Melo , et al. April 29, 1	1997-04-29
Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems Grant 5,553,310 - Taylor , et al. September 3, 1	1996-09-03
System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal Grant 5,553,248 - Melo , et al. September 3, 1	1996-09-03
Bus master arbitration circuitry having improved prioritization Grant 5,471,590 - Melo , et al. November 28, 1	1995-11-28
Password protected enhancement configuration register for addressing an increased number of adapter circuit boards with target machine emulation capabilities Grant 5,138,706 - Melo , et al. August 11, 1	1992-08-11

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