Meier; Peter J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Meier; Peter J..The latest application filed is for "low power parallelization to multiple output bus widths".

Company Profile

0.12.8

Meier; Peter J. - Fort Collins CO
Meier; Peter J. - Ft. Collins CO
Meier; Peter J - Fort Collins CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low power parallelization to multiple output bus widths Grant 9,767,062 - Miller , et al. September 19, 2	2017-09-19
Low Power Parallelization To Multiple Output Bus Widths App 20160306765 - Miller; Darrin C. ; et al.	2016-10-20
Modal PAM2/4 Pipelined Programmable Receiver Having Feed Forward Equalizer (FFE) And Decision Feedback Equalizer (DFE) Optimized For Forward Error Correction (FEC) Bit Error Rate (BER) Performance App 20150085914 - Kizer; Jade Michael ; et al.	2015-03-26
System and Method For Adaptive N-Phase Clock Generation For An N-Phase Receiver App 20140362962 - Meier; Peter J. ; et al.	2014-12-11
Modal PAM2/PAM4 Divide By N (Div-N) Automatic Correlation Engine (ACE) For A Receiver App 20140355658 - Meier; Peter J. ; et al.	2014-12-04
System and method for high speed data parallelization for an N-phase receiver Grant 8,902,091 - Miller , et al. December 2, 2	2014-12-02
Fast lock clock-data recovery for phase steps Grant 8,634,503 - Misek , et al. January 21, 2	2014-01-21
Fast Lock Clock-data Recovery For Phase Steps App 20120250811 - Misek; Brian J. ; et al.	2012-10-04
Integrated circuit design method for efficiently generating mask data Grant 7,526,744 - Martin , et al. April 28, 2	2009-04-28
Integrated Circuit Design Method for Efficiently Generating Mask Data App 20080184188 - Martin; Robert J. ; et al.	2008-07-31
Method and apparatus for synchronously transferring data across multiple clock domains Grant 6,744,285 - Mangum , et al. June 1, 2	2004-06-01
Method and apparatus for synchronously transferring data across multiple clock domains App 20040027166 - Mangum, Wayne G. ; et al.	2004-02-12
Self calibrating register for source synchronous clocking systems Grant 6,665,218 - Meier , et al. December 16, 2	2003-12-16
Self calibrating register for source synchronoous clocking systems App 20030102892 - Meier, Peter J. ; et al.	2003-06-05
Integrated circuit with alternately selectable state evaluation provisions Grant 6,539,507 - Juenemann , et al. March 25, 2	2003-03-25
Method and apparatus for low cost set mapping Grant 6,124,869 - Miller , et al. September 26, 2	2000-09-26
High voltage tolerant CMOS input/output pad circuits Grant 5,646,809 - Motley , et al. July 8, 1	1997-07-08
Method of programming a desired source resistance for a driver stage Grant 5,581,197 - Motley , et al. December 3, 1	1996-12-03
Quick resolving latch Grant 5,467,038 - Motley , et al. November 14, 1	1995-11-14

Company Registrations

SEC

0001382819

MEIER PETER J

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