| Patent | Date |
|---|
Zero-power programmable memory cell
Grant RE40,311 - Mehta , et al. May 13, 2 | 2008-05-13 |
EEPROM device with voltage-limiting charge pump circuit
Grant 7,242,053 - Mehta , et al. July 10, 2 | 2007-07-10 |
Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions
Grant 7,078,286 - Mehta July 18, 2 | 2006-07-18 |
Process for fabricating a semiconductor device having an RTCVD layer
App 20060128162 - Mehta; Sunil D. ; et al. | 2006-06-15 |
High-performance non-volatile memory device and fabrication process
Grant 6,977,408 - Lin , et al. December 20, 2 | 2005-12-20 |
Voltage limited EEPROM device and process for fabricating the device
Grant 6,846,714 - Mehta , et al. January 25, 2 | 2005-01-25 |
EEPROM device having an isolation-bounded tunnel capacitor and fabrication process
Grant 6,841,447 - Logie , et al. January 11, 2 | 2005-01-11 |
Device having electrically isolated low voltage and high voltage regions and process for fabricating the device
Grant 6,833,602 - Mehta December 21, 2 | 2004-12-21 |
EEPROM device having a retrograde program junction region and process for fabricating the device
Grant 6,716,705 - Mehta , et al. April 6, 2 | 2004-04-06 |
EEPROM device having improved data retention and process for fabricating the device
Grant 6,649,514 - Jiang , et al. November 18, 2 | 2003-11-18 |
EEPROM with a neutralized doping at tunnel window edge
Grant 6,600,188 - Jiang , et al. July 29, 2 | 2003-07-29 |
Shallow junction EEPROM device and process for fabricating the device
Grant 6,596,587 - Mehta July 22, 2 | 2003-07-22 |
Complementary avalanche injection EEPROM cell
Grant 6,570,212 - Mehta , et al. May 27, 2 | 2003-05-27 |
Combination of BPTEOS oxide film with CMP and RTA to achieve good data retention
Grant 6,524,911 - Mehta February 25, 2 | 2003-02-25 |
Combination Of Bpteos Oxide Film With Cmp And Rta To Achieve Good Data Retention
App 20030036230 - Mehta, Sunil D. | 2003-02-20 |
Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress
Grant 6,455,912 - Kim , et al. September 24, 2 | 2002-09-24 |
Farication Of High Quality Oxides By Controlling Spacing Between Semiconductor Wafers During Processing
App 20020019143 - KIM, HYEON-SEAG ; et al. | 2002-02-14 |
Eeprom Cell With Self-aligned Tunneling Window
App 20010042883 - LI, XIAO YU ; et al. | 2001-11-22 |
Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress
Grant 6,297,128 - Kim , et al. October 2, 2 | 2001-10-02 |
Gate isolated triple-well non-volatile cell
App 20010022359 - Mehta, Sunil D. | 2001-09-20 |
Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell
Grant 6,282,123 - Mehta August 28, 2 | 2001-08-28 |
Triple-well EEPROM cell using P-well for tunneling across a channel
Grant 6,274,898 - Mehta , et al. August 14, 2 | 2001-08-14 |
Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect
Grant 6,261,944 - Mehta , et al. July 17, 2 | 2001-07-17 |
Process for fabricating a high-endurance non-volatile memory device
Grant 6,255,169 - Li , et al. July 3, 2 | 2001-07-03 |
Reduction of mechanical stress in shallow trench isolation process
Grant 6,221,733 - Li , et al. April 24, 2 | 2001-04-24 |
Method of forming a non-volatile memory device
Grant 6,214,666 - Mehta April 10, 2 | 2001-04-10 |
Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb
Grant 6,208,559 - Tu , et al. March 27, 2 | 2001-03-27 |
Boron doped silicon capacitor plate
Grant 6,172,392 - Schmidt , et al. January 9, 2 | 2001-01-09 |
Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon
Grant 6,166,428 - Mehta , et al. December 26, 2 | 2000-12-26 |
Method for sorting semiconductor devices having a plurality of non-volatile memory cells
Grant 6,075,724 - Li , et al. June 13, 2 | 2000-06-13 |
Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss
Grant 6,071,784 - Mehta , et al. June 6, 2 | 2000-06-06 |
Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide
Grant 6,064,105 - Li , et al. May 16, 2 | 2000-05-16 |
Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers
Grant 6,060,766 - Mehta , et al. May 9, 2 | 2000-05-09 |
Method of selectively annealing damaged doped regions
Grant 6,040,019 - Ishida , et al. March 21, 2 | 2000-03-21 |
Non-volatile memory cell having dual avalanche injection elements
Grant 6,034,893 - Mehta March 7, 2 | 2000-03-07 |
Zero-power CMOS non-volatile memory cell having an avalanche injection element
Grant 6,028,789 - Mehta , et al. February 22, 2 | 2000-02-22 |
Method of programming and erasing an EEPROM device under an elevated temperature and apparatus thereof
Grant 6,009,033 - Li , et al. December 28, 1 | 1999-12-28 |
High integrity borderless vias with protective sidewall spacer
Grant 5,982,035 - Tran , et al. November 9, 1 | 1999-11-09 |
Oxide formation process for manufacturing programmable logic device
Grant 5,960,274 - Mehta September 28, 1 | 1999-09-28 |
Reduction of charge loss in nonvolatile memory cells by phosphorus implantation into PECVD nitride/oxynitride films
Grant 5,940,735 - Mehta , et al. August 17, 1 | 1999-08-17 |
Method and apparatus incorporating nitrogen selectively for differential oxide growth
Grant 5,904,575 - Ishida , et al. May 18, 1 | 1999-05-18 |
Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide
Grant 5,854,114 - Li , et al. December 29, 1 | 1998-12-29 |
Simplified masking process for programmable logic device manufacture
Grant 5,830,795 - Mehta , et al. November 3, 1 | 1998-11-03 |
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