Mehta; Anup S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mehta; Anup S..The latest application filed is for "ir drop analysis in integrated circuit timing".

Company Profile

0.11.7

Mehta; Anup S. - Fremont CA
Mehta; Anup S. - Santa Clara CA
Mehta; Anup S. - Folsom CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
IR(voltage) drop analysis in integrated circuit timing Grant 8,712,752 - Lau , et al. April 29, 2	2014-04-29
IR Drop Analysis in Integrated Circuit Timing App 20120215516 - Lau; Betty Y. ; et al.	2012-08-23
Efficient encoding for detecting load dependency on store with misalignment Grant 7,996,646 - Yeh , et al. August 9, 2	2011-08-09
Efficient Encoding for Detecting Load Dependency on Store with Misalignment App 20100169619 - Yeh; Tse-yu ; et al.	2010-07-01
Efficient encoding for detecting load dependency on store with misalignment Grant 7,721,066 - Yeh , et al. May 18, 2	2010-05-18
Efficient Encoding for Detecting Load Dependency on Store with Misalignment App 20080307173 - Yeh; Tse-yu ; et al.	2008-12-11
Modified glitch latch for use with power saving dynamic register file structures Grant 6,981,169 - Chandran , et al. December 27, 2	2005-12-27
Modified retirement payload array Grant 6,870,789 - Chandran , et al. March 22, 2	2005-03-22
Dynamic Circuitry With On-chip Temperature-controlled Keeper Device App 20040130350 - Desai, Shaishav A. ; et al.	2004-07-08
Dynamic circuitry with on-chip temperature-controlled keeper device Grant 6,759,877 - Desai , et al. July 6, 2	2004-07-06
Multiple discharge capable bit line Grant 6,654,301 - Chehrazi , et al. November 25, 2	2003-11-25
Modified glitch latch for use with power saving dynamic register file structures App 20030163749 - Chandran, Arjun P. ; et al.	2003-08-28
Power savings in dynamic register file structures App 20030154365 - Chandran, Arjun P. ; et al.	2003-08-14
Multiple discharge capable bit line App 20030058721 - Chehrazi, Farzad ; et al.	2003-03-27
Secondary precharge mechanism for high speed multi-ported register files Grant 6,466,497 - Desai , et al. October 15, 2	2002-10-15
Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanism Grant 6,222,404 - Mehta , et al. April 24, 2	2001-04-24
Programmable clock circuit Grant 5,345,109 - Mehta September 6, 1	1994-09-06

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