Mehrad; Freidoon

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mehrad; Freidoon.The latest application filed is for "method to attain low defectivity fully silicided gates".

Company Profile

0.42.45

Mehrad; Freidoon - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device Grant 8,574,980 - Mehrad , et al. November 5, 2	2013-11-05
Gate dielectric first replacement gate processes and integrated circuits therefrom Grant 8,372,703 - Kirkpatrick , et al. February 12, 2	2013-02-12
Method to attain low defectivity fully silicided gates Grant 8,273,645 - Visokay , et al. September 25, 2	2012-09-25
Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flow Grant 7,960,280 - Mehrad , et al. June 14, 2	2011-06-14
Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom Grant 7,943,456 - Yu , et al. May 17, 2	2011-05-17
Method To Attain Low Defectivity Fully Silicided Gates App 20110097884 - VISOKAY; Mark Robert ; et al.	2011-04-28
Reducing gate CD bias in CMOS processing Grant 7,910,422 - Mehrad , et al. March 22, 2	2011-03-22
Method for forming CMOS transistors having FUSI gate electrodes and targeted work functions Grant 7,892,906 - Mehrad , et al. February 22, 2	2011-02-22
Gate Dielectric First Replacement Gate Processes And Integrated Circuits Therefrom App 20110031557 - Kirkpatrick; Brian K. ; et al.	2011-02-10
Gate dielectric first replacement gate processes and integrated circuits therefrom Grant 7,838,356 - Kirkpatrick , et al. November 23, 2	2010-11-23
Method of forming a silicided gate utilizing a CMP stack Grant 7,763,540 - Johnson , et al. July 27, 2	2010-07-27
Method Of Simultaneously Siliciding A Polysilicon Gate And Source/drain Of A Semiconductor Device, And Related Device App 20100176462 - Mehrad; Freidoon ; et al.	2010-07-15
Method For Integration Of Replacement Gate In Cmos Flow App 20100164008 - Mehrad; Freidoon ; et al.	2010-07-01
Gate Dielectric First Replacement Gate Processes And Integrated Circuits Therefrom App 20100164006 - KIRKPATRICK; BRIAN K. ; et al.	2010-07-01
Selective Wet Etch Process For Cmos Ics Having Embedded Strain Inducing Regions And Integrated Circuits Therefrom App 20100164005 - YU; SHAOFENG ; et al.	2010-07-01
Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device Grant 7,727,842 - Mehrad , et al. June 1, 2	2010-06-01
Method of manufacturing metal silicide contacts Grant 7,670,952 - Obeng , et al. March 2, 2	2010-03-02
Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, and Related Device App 20090321846 - Mehrad; Freidoon ; et al.	2009-12-31
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance Grant 7,601,575 - Bu , et al. October 13, 2	2009-10-13
Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device Grant 7,585,738 - Yu , et al. September 8, 2	2009-09-08
Method for Forming CMOS Transistors Having FUSI Gate Electrodes and Targeted Work Functions App 20090191675 - Mehrad; Freidoon ; et al.	2009-07-30
Reducing Gate Cd Bias In Cmos Processing App 20090166629 - Mehrad; Freidoon ; et al.	2009-07-02
Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits Grant 7,504,339 - Chen , et al. March 17, 2	2009-03-17
Method Of Forming Fully Silicided Nmos And Pmos Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, And Related Device App 20090057776 - Mehrad; Freidoon ; et al.	2009-03-05
Process Method To Fully Salicide (fusi) Both N-poly And P-poly On A Cmos Flow App 20090050976 - Mehrad; Freidoon ; et al.	2009-02-26
Process method to facilitate silicidation Grant 7,448,395 - Lu , et al. November 11, 2	2008-11-11
Method of Forming a Silicided Gate Utilizing a CMP Stack App 20080268631 - Johnson; Frank Scott ; et al.	2008-10-30
Method Of Forming A Fully Silicided Semiconductor Device With Independent Gate And Source/drain Doping And Related Device App 20080265420 - Yu; Shaofeng ; et al.	2008-10-30
Method of Forming a Fully Silicided Semiconductor Device with Independent Gate and Source/Drain Doping and Related Device App 20080265345 - Yu; Shaofeng ; et al.	2008-10-30
Method Of Simultaneously Siliciding A Polysilicon Gate And Source/drain Of A Semiconductor Device, And Related Device App 20080265344 - Mehrad; Freidoon ; et al.	2008-10-30
Method Of Manufacturing Metal Silicide Contacts App 20080230846 - Obeng; Yaw S. ; et al.	2008-09-25
Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process App 20080233747 - Choi; Jinhan ; et al.	2008-09-25
Process method to optimize fully silicided gate (FUSI) thru PAI implant App 20080206973 - Johnson; Frank Scott ; et al.	2008-08-28
Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes App 20080176345 - Yu; Shaofeng ; et al.	2008-07-24
Method to obtain fully silicided poly gate Grant 7,396,716 - Mehrad , et al. July 8, 2	2008-07-08
Method to obtain fully silicided gate electrodes Grant 7,244,642 - Vitale , et al. July 17, 2	2007-07-17
Method to obtain fully silicided gate electrodes App 20070066007 - Vitale; Steven A. ; et al.	2007-03-22
Method to obtain fully silicided poly gate App 20070037342 - Mehrad; Freidoon ; et al.	2007-02-15
Multi-layer reducible sidewall process Grant 7,112,497 - Mehrad , et al. September 26, 2	2006-09-26
Method for forming MOS transistors with improved sidewall structures Grant 7,078,347 - Mehrad , et al. July 18, 2	2006-07-18
Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) Grant 7,045,410 - Mehrad , et al. May 16, 2	2006-05-16
Multi-doped semiconductor e-fuse App 20060065946 - Mehrad; Freidoon ; et al.	2006-03-30
Thermal oxidation for improved silicide formation App 20060057853 - Mehrotra; Manoj ; et al.	2006-03-16
Method to design for or modulate the CMOS transistor inverse narrow width effect (INWE) using shallow trench isolation (STI) App 20060024911 - Mehrad; Freidoon ; et al.	2006-02-02
Process method to facilitate silicidation App 20060014393 - Lu; Jiong-Ping ; et al.	2006-01-19
Multi-layer reducible sidewall process App 20050287751 - Mehrad, Freidoon ; et al.	2005-12-29
Shallow trench isolation structure and method App 20050247994 - Mehrad, Freidoon ; et al.	2005-11-10
Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits App 20050208732 - Chen, Zhihao ; et al.	2005-09-22
Shallow trench isolation structure and method Grant 6,930,018 - Mehrad , et al. August 16, 2	2005-08-16
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance Grant 6,930,007 - Bu , et al. August 16, 2	2005-08-16
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance App 20050164431 - Bu, Haowen ; et al.	2005-07-28
Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits Grant 6,917,093 - Chen , et al. July 12, 2	2005-07-12
Forming a trench to define one or more isolation regions in a semiconductor structure Grant 6,905,943 - DeLoach , et al. June 14, 2	2005-06-14
Flash memory array structure and method of forming Grant 6,897,516 - Mehrad , et al. May 24, 2	2005-05-24
Forming A Trench To Define One Or More Isolation Regions In A Semiconductor Structure App 20050101101 - DeLoach, Juanita ; et al.	2005-05-12
Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits App 20050062127 - Chen, Zhihao ; et al.	2005-03-24
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance App 20050059228 - Bu, Haowen ; et al.	2005-03-17
Method to improve STI nano gap fill and moat nitride pull back Grant 6,828,213 - Mehrad , et al. December 7, 2	2004-12-07
Semiconductor device isolation structure and method of forming App 20040238915 - Chen, Zhihao ; et al.	2004-12-02
Method for moat nitride pull back for shallow trench isolation Grant 6,818,526 - Mehrad , et al. November 16, 2	2004-11-16
Method to salicide source-line in flash memory with STI Grant 6,803,273 - Ambrose , et al. October 12, 2	2004-10-12
Method for forming MOS transistors with improved sidewall structures App 20040175911 - Mehrad, Freidoon ; et al.	2004-09-09
Flash memory cell process using a hardmask Grant 6,784,056 - Schneider , et al. August 31, 2	2004-08-31
Implanted vertical source-line under straight stack for flash eprom Grant 6,765,257 - Mehrad , et al. July 20, 2	2004-07-20
Semiconductor device isolation structure and method of forming Grant 6,737,333 - Chen , et al. May 18, 2	2004-05-18
Flash memory cell process using a hardmask App 20040085830 - Schneider, Paul A. ; et al.	2004-05-06
Multi-layer silicide block process Grant 6,730,554 - Baldwin , et al. May 4, 2	2004-05-04
Method for moat nitride pull back for shallow trench isolation App 20040067620 - Mehrad, Freidoon ; et al.	2004-04-08
Transistor formed from stacked disposable sidewall spacer Grant 6,706,605 - Ekbote , et al. March 16, 2	2004-03-16
Shallow trench isolation structure and method App 20040014291 - Mehrad, Freidoon ; et al.	2004-01-22
Shallow trench isolation step height detection method Grant 6,677,766 - Mehrad , et al. January 13, 2	2004-01-13
Flash memory cell process using a hardmask Grant 6,667,210 - Schneider , et al. December 23, 2	2003-12-23
Flash memory array structure and method of forming App 20030207527 - Mehrad, Freidoon ; et al.	2003-11-06
Method to improve STI nano gap fill and moat nitride pull back App 20030181022 - Mehrad, Freidoon ; et al.	2003-09-25
Semiconductor device isolation structure and method of forming App 20030006476 - Chen, Zhihao ; et al.	2003-01-09
Flash memory array structure and method of forming App 20030006448 - Mehrad, Freidoon ; et al.	2003-01-09
Flash memory cell process using a hardmask App 20020127800 - Schneider, Paul A. ; et al.	2002-09-12
Hard-mask etch process App 20020072225 - Laaksonen, Reima T. ; et al.	2002-06-13
Shallow trench isolation step height detection method App 20020060575 - Mehrad, Freidoon ; et al.	2002-05-23
Sidewall process to improve the flash memory cell performance App 20020055228 - Ambrose, Thomas M. ; et al.	2002-05-09
Method to reduce source-line resistance in flash memory with sti Grant 6,306,737 - Mehrad , et al. October 23, 2	2001-10-23
Nonvolatile memory cell with P-N junction formed in polysilicon floating gate Grant 5,753,952 - Mehrad May 19, 1	1998-05-19
Nonvolatile memory array with compatible vertical source lines Grant 5,659,500 - Mehrad August 19, 1	1997-08-19
Channel-stop process for use with thick-field isolation regions in triple-well structures Grant 5,604,150 - Mehrad February 18, 1	1997-02-18
Extended-life method for soft-programming floating-gate memory cells Grant 5,576,992 - Mehrad November 19, 1	1996-11-19

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