| Patent | Date |
|---|
Fin Doping And Integrated Circuit Structures Resulting Therefrom
App 20220310601 - LILAK; Aaron D. ; et al. | 2022-09-29 |
Non-silicon N-type And P-type Stacked Transistors For Integrated Circuit Devices
App 20220310605 - Dewey; Gilbert ; et al. | 2022-09-29 |
Multi-height finfet device by selective oxidation
Grant 11,456,372 - Kim , et al. September 27, 2 | 2022-09-27 |
Deep Trench Via For Three-dimensional Integrated Circuit
App 20220285342 - WANG; Yih ; et al. | 2022-09-08 |
Buried etch-stop layer to help control transistor source/drain depth
Grant 11,430,868 - Mehandru , et al. August 30, 2 | 2022-08-30 |
Transistor Cells Including A Deep Via Lined With A Dielectric Material
App 20220254681 - Morrow; Patrick ; et al. | 2022-08-11 |
Double gated thin film transistors
Grant 11,411,119 - Lilak , et al. August 9, 2 | 2022-08-09 |
Gate-all-around Integrated Circuit Structures Having Insulator Fin On Insulator Substrate
App 20220246743 - LILAK; Aaron D. ; et al. | 2022-08-04 |
Isolation Schemes For Gate-all-around Transistor Devices
App 20220246759 - MEHANDRU; Rishabh ; et al. | 2022-08-04 |
Vertically stacked finFETs and shared gate patterning
Grant 11,404,319 - Lilak , et al. August 2, 2 | 2022-08-02 |
Heterogeneous Ge/III-V CMOS transistor structures
Grant 11,398,479 - Rachmady , et al. July 26, 2 | 2022-07-26 |
Stacked transistors with Si PMOS and high mobility thin film transistor NMOS
Grant 11,393,818 - Dewey , et al. July 19, 2 | 2022-07-19 |
Isolation wall stressor structures to improve channel stress and their methods of fabrication
Grant 11,393,722 - Lilak , et al. July 19, 2 | 2022-07-19 |
Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices
Grant 11,387,238 - Dewey , et al. July 12, 2 | 2022-07-12 |
Source or drain structures with contact etch stop layer
Grant 11,374,100 - Bomberger , et al. June 28, 2 | 2022-06-28 |
Deep trench via for three-dimensional integrated circuit
Grant 11,373,999 - Wang , et al. June 28, 2 | 2022-06-28 |
Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor
Grant 11,374,024 - Lilak , et al. June 28, 2 | 2022-06-28 |
Pedestal fin structure for stacked transistor integration
Grant 11,374,004 - Lilak , et al. June 28, 2 | 2022-06-28 |
Stacked nanowire transistor structure with different channel geometries for stress
Grant 11,367,722 - Lilak , et al. June 21, 2 | 2022-06-21 |
Stacked self-aligned transistors with single workfunction metal
Grant 11,362,189 - Lilak , et al. June 14, 2 | 2022-06-14 |
Contact Architecture For Capacitance Reduction And Satisfactory Contact Resistance
App 20220165855 - MEHANDRU; Rishabh ; et al. | 2022-05-26 |
Gate-all-around integrated circuit structures having insulator fin on insulator substrate
Grant 11,342,432 - Lilak , et al. May 24, 2 | 2022-05-24 |
Transistor Contact Area Enhancement
App 20220157984 - MEHANDRU; Rishabh ; et al. | 2022-05-19 |
Isolation schemes for gate-all-around transistor devices
Grant 11,335,807 - Mehandru , et al. May 17, 2 | 2022-05-17 |
Thin Film Transistors Having U-shaped Features
App 20220149209 - DEWEY; Gilbert ; et al. | 2022-05-12 |
Transistor cells including a deep via lined wit h a dielectric material
Grant 11,328,951 - Morrow , et al. May 10, 2 | 2022-05-10 |
Device Isolation
App 20220140143 - Mehandru; Rishabh ; et al. | 2022-05-05 |
Stacked Transistors
App 20220123128 - MORROW; Patrick ; et al. | 2022-04-21 |
Isolation Walls For Vertically Stacked Transistor Structures
App 20220115372 - LILAK; Aaron ; et al. | 2022-04-14 |
Substrate-free Integrated Circuit Structures
App 20220102385 - GUHA; Biswajeet ; et al. | 2022-03-31 |
Forksheet Transistor Architectures
App 20220102346 - LILAK; Aaron D. ; et al. | 2022-03-31 |
Wrap-around Contact Structures For Semiconductor Fins
App 20220093460 - MEHANDRU; Rishabh | 2022-03-24 |
Dynamic logic built with stacked transistors sharing a common gate
Grant 11,282,861 - Nelson , et al. March 22, 2 | 2022-03-22 |
Contact architecture for capacitance reduction and satisfactory contact resistance
Grant 11,282,930 - Mehandru , et al. March 22, 2 | 2022-03-22 |
Transistor contact area enhancement
Grant 11,276,780 - Mehandru , et al. March 15, 2 | 2022-03-15 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20220069094 - MORROW; Patrick ; et al. | 2022-03-03 |
Semiconductor diodes employing back-side semiconductor or metal
Grant 11,264,405 - Morrow , et al. March 1, 2 | 2022-03-01 |
Thin film transistors having U-shaped features
Grant 11,264,512 - Dewey , et al. March 1, 2 | 2022-03-01 |
Device, method and system for promoting channel stress in a NMOS transistor
Grant 11,264,501 - Mehandru , et al. March 1, 2 | 2022-03-01 |
Device isolation
Grant 11,264,500 - Mehandru , et al. March 1, 2 | 2022-03-01 |
Stacked transistors
Grant 11,257,929 - Morrow , et al. February 22, 2 | 2022-02-22 |
Forksheet transistor architectures
Grant 11,239,236 - Lilak , et al. February 1, 2 | 2022-02-01 |
Isolation walls for vertically stacked transistor structures
Grant 11,239,232 - Lilak , et al. February 1, 2 | 2022-02-01 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20220028779 - Morrow; Patrick ; et al. | 2022-01-27 |
Wrap-around contact structures for semiconductor fins
Grant 11,227,799 - Mehandru January 18, 2 | 2022-01-18 |
Field Effect Transistor Having A Gate Dielectric With A Dipole Layer And Having A Gate Stressor Layer
App 20210408282 - TIWARI; Vishal ; et al. | 2021-12-30 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 11,201,221 - Morrow , et al. December 14, 2 | 2021-12-14 |
Stacked Transistors With Contact Last
App 20210384191 - Pillarisetty; Ravi ; et al. | 2021-12-09 |
Three-dimensional Nanoribbon-based Two-transistor Memory Cells
App 20210375926 - Mehandru; Rishabh ; et al. | 2021-12-02 |
Vertically Stacked Transistors In A Fin
App 20210351078 - Lilak; Aaron D. ; et al. | 2021-11-11 |
Metallization Structures Under A Semiconductor Device Layer
App 20210343710 - Lilak; Aaron D. ; et al. | 2021-11-04 |
Semiconductor device having stacked transistors and multiple threshold voltage control
Grant 11,152,396 - Lilak , et al. October 19, 2 | 2021-10-19 |
Semiconductor layer between source/drain regions and gate spacers
Grant 11,152,461 - Mehandru , et al. October 19, 2 | 2021-10-19 |
Integrated circuit device with crenellated metal trace layout
Grant 11,139,241 - Morrow , et al. October 5, 2 | 2021-10-05 |
Gate-all-around Integrated Circuit Structures Having Insulator Fin On Insulator Substrate
App 20210305388 - LILAK; Aaron D. ; et al. | 2021-09-30 |
Forksheet Transistor Architectures
App 20210296315 - LILAK; Aaron D. ; et al. | 2021-09-23 |
Systems and methods to reduce FinFET gate capacitance
Grant 11,107,924 - Lilak , et al. August 31, 2 | 2021-08-31 |
Metallization structures under a semiconductor device layer
Grant 11,107,811 - Lilak , et al. August 31, 2 | 2021-08-31 |
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
Grant 11,094,831 - Mehandru , et al. August 17, 2 | 2021-08-17 |
Source contact and channel interface to reduce body charging from band-to-band tunneling
Grant 11,094,716 - Basu , et al. August 17, 2 | 2021-08-17 |
Stacked transistor architecture having diverse fin geometry
Grant 11,075,198 - Lilak , et al. July 27, 2 | 2021-07-27 |
Vertically stacked transistors in a pin
Grant 11,075,119 - Lilak , et al. July 27, 2 | 2021-07-27 |
Bottom fin trim isolation aligned with top gate for stacked device architectures
Grant 11,075,202 - Lilak , et al. July 27, 2 | 2021-07-27 |
Method, device and system to provide capacitance for a dynamic random access memory cell
Grant 11,049,861 - Lilak , et al. June 29, 2 | 2021-06-29 |
Integrated Circuit Device Structures And Double-sided Electrical Testing
App 20210175124 - RAO; Valluri R. ; et al. | 2021-06-10 |
Fin Shaping And Integrated Circuit Structures Resulting Therefrom
App 20210167209 - LIAO; Szuya S. ; et al. | 2021-06-03 |
Removal Of A Bottom-most Nanowire From A Nanowire Device Stack
App 20210159312 - Lilak; Aaron ; et al. | 2021-05-27 |
Techniques for increasing channel region tensile strain in n-MOS devices
Grant 11,011,620 - Mehandru , et al. May 18, 2 | 2021-05-18 |
Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability
Grant 11,011,537 - Lilak , et al. May 18, 2 | 2021-05-18 |
Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing
Grant 10,991,696 - Lilak , et al. April 27, 2 | 2021-04-27 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20210111115 - Morrow; Patrick ; et al. | 2021-04-15 |
Methods and apparatus to remove epitaxial defects in semiconductors
Grant 10,978,590 - Lilak , et al. April 13, 2 | 2021-04-13 |
Stacked Transistors With Si Pmos And High Mobility Thin Film Transistor Nmos
App 20210091080 - DEWEY; Gilbert ; et al. | 2021-03-25 |
Device, Method And System To Provide A Stressed Channel Of A Transistor
App 20210083117 - Mehandru; Rishabh ; et al. | 2021-03-18 |
Bottom Fin Trim Isolation Aligned With Top Gate For Stacked Device Architectures
App 20210074704 - Lilak; Aaron D. ; et al. | 2021-03-11 |
Methods and apparatus for gettering impurities in semiconductors
Grant 10,937,665 - Lilak , et al. March 2, 2 | 2021-03-02 |
Iii-v Source/drain In Top Nmos Transistors For Low Temperature Stacked Transistor Contacts
App 20210057413 - DEWEY; Gilbert ; et al. | 2021-02-25 |
Contact Architecture For Capacitance Reduction And Satisfactory Contact Resistance
App 20210050423 - MEHANDRU; Rishabh ; et al. | 2021-02-18 |
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20210043755 - MEHANDRU; Rishabh ; et al. | 2021-02-11 |
Backside fin recess control with multi-HSI option
Grant 10,910,405 - Lilak , et al. February 2, 2 | 2021-02-02 |
Semiconductor device contacts with increased contact area
Grant 10,896,963 - Mehandru , et al. January 19, 2 | 2021-01-19 |
Retrograde transistor doping by heterojunction materials
Grant 10,896,907 - Keys , et al. January 19, 2 | 2021-01-19 |
Removal of a bottom-most nanowire from a nanowire device stack
Grant 10,892,326 - Lilak , et al. January 12, 2 | 2021-01-12 |
Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices
Grant 10,886,272 - Cea , et al. January 5, 2 | 2021-01-05 |
Integrated circuit device with back-side interconnection to deep source/drain semiconductor
Grant 10,886,217 - Morrow , et al. January 5, 2 | 2021-01-05 |
Improved Contacts To N-type Transistors With L-valley Channels
App 20200411690 - Crum; Dax M. ; et al. | 2020-12-31 |
Sub-fin Leakage Reduction For Template Strained Materials
App 20200411640 - MEHANDRU; Rishabh ; et al. | 2020-12-31 |
Amorphization And Regrowth Of Source-drain Regions From The Bottom-side Of A Semiconductor Assembly
App 20200411644 - LILAK; Aaron ; et al. | 2020-12-31 |
Sideways Vias In Isolation Areas To Contact Interior Layers In Stacked Devices
App 20200411430 - MANNEBACH; Ehren ; et al. | 2020-12-31 |
Substrate-less Finfet Diode Architectures With Backside Metal Contact And Subfin Regions
App 20200403007 - THOMSON; Nicholas ; et al. | 2020-12-24 |
Contact architecture for capacitance reduction and satisfactory contact resistance
Grant 10,872,960 - Mehandru , et al. December 22, 2 | 2020-12-22 |
Integrated circuit structures
Grant 10,872,820 - Block , et al. December 22, 2 | 2020-12-22 |
Inverted staircase contact for density improvement to 3D stacked devices
Grant 10,861,870 - Lilak , et al. December 8, 2 | 2020-12-08 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20200381525 - MORROW; Patrick ; et al. | 2020-12-03 |
Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Grant 10,847,635 - Mehandru , et al. November 24, 2 | 2020-11-24 |
Non-silicon N-type And P-type Stacked Transistors For Integrated Circuit Devices
App 20200335501 - Dewey; Gilbert ; et al. | 2020-10-22 |
Heterogeneous Ge/iii-v Cmos Transistor Structures
App 20200312846 - Rachmady; Willy ; et al. | 2020-10-01 |
Stacked channel structures for MOSFETs
Grant 10,790,281 - Mehandru , et al. September 29, 2 | 2020-09-29 |
Deep Source & Drain For Transistor Structures With Back-side Contact Metallization
App 20200303509 - MEHANDRU; Rishabh ; et al. | 2020-09-24 |
Capacitance Reduction For Semiconductor Devices Based On Wafer Bonding
App 20200303238 - MANNEBACH; Ehren ; et al. | 2020-09-24 |
Isolation Wall Stressor Structures To Improve Channel Stress And Their Methods Of Fabrication
App 20200303257 - Lilak; Aaron D. ; et al. | 2020-09-24 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 10,784,358 - Morrow , et al. Sept | 2020-09-22 |
Stacked Transistors With Different Crystal Orientations In Different Device Strata
App 20200295127 - Mannebach; Ehren ; et al. | 2020-09-17 |
Nanowire transistor device architectures
Grant 10,770,458 - Mehandru , et al. Sep | 2020-09-08 |
Source Contact And Channel Interface To Reduce Body Charging From Band-to-band Tunneling
App 20200279872 - BASU; Dipanjan ; et al. | 2020-09-03 |
Stacked Transistors With Dielectric Between Channels Of Different Device Strata
App 20200266218 - Lilak; Aaron D. ; et al. | 2020-08-20 |
Vertical Diode In Stacked Transistor Architecture
App 20200258881 - A1 | 2020-08-13 |
Semiconductor Device Having Stacked Transistors And Multiple Threshold Voltage Control
App 20200251502 - Kind Code | 2020-08-06 |
Integrated Circuits With Stacked Transistors And Methods Of Manufacturing The Same Using Processes Which Fabricate Lower Gate St
App 20200235134 - Lilak; Aaron D. ; et al. | 2020-07-23 |
Stacked Transistor Architecture Having Diverse Fin Geometry
App 20200235092 - Lilak; Aaron D. ; et al. | 2020-07-23 |
Vertically Stacked Finfets & Shared Gate Patterning
App 20200235013 - Lilak; Aaron ; et al. | 2020-07-23 |
Device, Method And System For Promoting Channel Stress In A Nmos Transistor
App 20200227558 - Mehandru; Rishabh ; et al. | 2020-07-16 |
Device, Method And System For Imposing Transistor Channel Stress With An Insulation Structure
App 20200227556 - Mehandru; Rishabh | 2020-07-16 |
Wrap-around Contact Structures For Semiconductor Nanowires And Nanoribbons
App 20200219997 - MEHANDRU; Rishabh ; et al. | 2020-07-09 |
Backside Fin Recess Control With Multi-hsi Option
App 20200176482 - LILAK; Aaron D. ; et al. | 2020-06-04 |
Metallization Structures Under A Semiconductor Device Layer
App 20200161298 - Lilak; Aaron D. ; et al. | 2020-05-21 |
Integrated Circuit Contact Structures
App 20200152750 - Morrow; Patrick ; et al. | 2020-05-14 |
Deep EPI enabled by backside reveal for stress enhancement and contact
Grant 10,636,907 - Lilak , et al. | 2020-04-28 |
Stacked Self-aligned Transistors With Single Workfunction Metal
App 20200105891 - LILAK; Aaron ; et al. | 2020-04-02 |
Gate-all-around Integrated Circuit Structures Having Vertically Discrete Source Or Drain Structures
App 20200105871 - GLASS; Glenn ; et al. | 2020-04-02 |
Gate-all-around Integrated Circuit Structures Having High Mobility
App 20200105753 - KOTLYAR; Roza ; et al. | 2020-04-02 |
Integrated Circuit Structures Having Asymmetric Source And Drain Structures
App 20200105759 - BOWONDER; Anupama ; et al. | 2020-04-02 |
Vertically Stacked Cmos With Upfront M0 Interconnect
App 20200098921 - RACHMADY; Willy ; et al. | 2020-03-26 |
Stacked Nanowire Transistor Structure With Different Channel Geometries For Stress
App 20200098756 - Lilak; Aaron ; et al. | 2020-03-26 |
Backside fin recess control with multi-hsi option
Grant 10,600,810 - Lilak , et al. | 2020-03-24 |
Contact Architecture For Capacitance Reduction And Satisfactory Contact Resistance
App 20200066851 - MEHANDRU; Rishabh ; et al. | 2020-02-27 |
Backside isolation for integrated circuit
Grant 10,573,715 - Lilak , et al. Feb | 2020-02-25 |
Device Isolation
App 20200052117 - Mehandru; Rishabh ; et al. | 2020-02-13 |
Integrated Circuit Device Structures And Double-sided Fabrication Techniques
App 20200035560 - BLOCK; Bruce ; et al. | 2020-01-30 |
Integrated circuit with stacked transistor devices
Grant 10,546,873 - Mehandru , et al. Ja | 2020-01-28 |
Semiconductor Nanowire Device Having Cavity Spacer And Method Of Fabricating Cavity Spacer For Semiconductor Nanowire Device
App 20200013905 - MEHANDRU; Rishabh ; et al. | 2020-01-09 |
Long channel MOS transistors for low leakage applications on a short channel CMOS chip
Grant 10,529,827 - Mehandru , et al. J | 2020-01-07 |
Interconnect Techniques For Electrically Connecting Source/drain Regions Of Stacked Transistors
App 20200006329 - LILAK; AARON D. ; et al. | 2020-01-02 |
Pedestal Fin Structure For Stacked Transistor Integration
App 20200006340 - LILAK; AARON D. ; et al. | 2020-01-02 |
Isolation Schemes For Gate-all-around Transistor Devices
App 20200006559 - MEHANDRU; RISHABH ; et al. | 2020-01-02 |
Transistor Contact Area Enhancement
App 20200006546 - MEHANDRU; Rishabh ; et al. | 2020-01-02 |
Source Or Drain Structures With Contact Etch Stop Layer
App 20200006504 - BOMBERGER; Cory ; et al. | 2020-01-02 |
Thin Film Transistors Having U-shaped Features
App 20200006575 - DEWEY; Gilbert ; et al. | 2020-01-02 |
Double Gated Thin Film Transistors
App 20200006573 - LILAK; Aaron ; et al. | 2020-01-02 |
Buried Etch-stop Layer To Help Control Transistor Source/drain Depth
App 20200006488 - MEHANDRU; RISHABH ; et al. | 2020-01-02 |
Techniques For Forming Gate Structures For Transistors Arranged In A Stacked Configuration On A Single Fin Structure
App 20200006331 - LILAK; AARON D. ; et al. | 2020-01-02 |
Isolation Walls For Vertically Stacked Transistor Structures
App 20190393214 - LILAK; Aaron ; et al. | 2019-12-26 |
Deep Trench Via For Three-dimensional Integrated Circuit
App 20190378836 - WANG; Yih ; et al. | 2019-12-12 |
Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices
Grant 10,497,781 - Lilak , et al. De | 2019-12-03 |
Dynamic Logic Built With Stacked Transistors Sharing A Common Gate
App 20190355756 - NELSON; Donald W. ; et al. | 2019-11-21 |
Semiconductor Layer Between Source/drain Regions And Gate Spacers
App 20190355811 - Mehandru; Rishabh ; et al. | 2019-11-21 |
Systems And Methods To Reduce Finfet Gate Capacitance
App 20190348535 - Lilak; Aaron D. ; et al. | 2019-11-14 |
Direct Self Assembly (dsa) Processing Of Vertically Stacked Devices With Self-aligned Regions
App 20190341384 - Lilak; Aaron D. ; et al. | 2019-11-07 |
Back Side Processing Of Integrated Circuit Structures To Form Insulation Structure Between Adjacent Transistor Structures
App 20190341297 - LILAK; AARON D. ; et al. | 2019-11-07 |
Isolation structures for an integrated circuit element and method of making same
Grant 10,468,489 - Lilak , et al. No | 2019-11-05 |
Removal Of A Bottom-most Nanowire From A Nanowire Device Stack
App 20190333990 - Lilak; Aaron ; et al. | 2019-10-31 |
Techniques For Forming Dual-strain Fins For Co-integrated N-mos And P-mos Devices
App 20190326290 - CEA; STEPHEN M. ; et al. | 2019-10-24 |
Vertically Stacked Transistors In A Pin
App 20190326175 - Lilak; Aaron D. ; et al. | 2019-10-24 |
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
Grant 10,453,967 - Mehandru , et al. Oc | 2019-10-22 |
Wrap-around Contact Structures For Semiconductor Fins
App 20190311950 - MEHANDRU; Rishabh | 2019-10-10 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20190312023 - Morrow; Patrick ; et al. | 2019-10-10 |
Nanowire Transistor Device Architectures
App 20190279978 - MEHANDRU; RISHABH ; et al. | 2019-09-12 |
Hybrid trigate and nanowire CMOS device architecture
Grant 10,411,090 - Weber , et al. Sept | 2019-09-10 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20190259699 - Morrow; Patrick ; et al. | 2019-08-22 |
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20190252525 - MEHANDRU; Rishabh ; et al. | 2019-08-15 |
Retrograde Transistor Doping By Heterojunction Materials
App 20190237466 - KEYS; Patrick H. ; et al. | 2019-08-01 |
Vertical Interconnect Methods For Stacked Device Architectures Using Direct Self Assembly With High Operational Parallelization
App 20190221577 - LILAK; Aaron D. ; et al. | 2019-07-18 |
Techniques For Increasing Channel Region Tensile Strain In N-mos Devices
App 20190207015 - MEHANDRU; RISHABH ; et al. | 2019-07-04 |
Stacked Transistors With Different Gate Lengths In Different Device Strata
App 20190196830 - Lilak; Aaron D. ; et al. | 2019-06-27 |
Inverted Staircase Contact For Density Improvement To 3d Stacked Devices
App 20190189635 - Lilak; Aaron ; et al. | 2019-06-20 |
Methods And Apparatus For Gettering Impurities In Semiconductors
App 20190189464 - Lilak; Aaron D. ; et al. | 2019-06-20 |
Methods And Apparatus To Remove Epitaxial Defects In Semiconductors
App 20190189795 - Lilak; Aaron D. ; et al. | 2019-06-20 |
Finfet Transistor With Channel Stress Induced Via Stressor Material Inserted Into Fin Plug Region Enabled By Backside Reveal
App 20190172950 - LILAK; Aaron D. ; et al. | 2019-06-06 |
Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Grant 10,304,946 - Mehandru , et al. | 2019-05-28 |
Semiconductor Diodes Employing Back-side Seimconductor Or Metal
App 20190096917 - Morrow; Patrick ; et al. | 2019-03-28 |
Transistor Cells Including A Deep Via Lined With A Dielectric Material
App 20190067091 - Morrow; Patrick ; et al. | 2019-02-28 |
Backside Fin Recess Control With Multi-hsi Option
App 20190027503 - LILAK; Aaron D. ; et al. | 2019-01-24 |
Integrated Circuit With Stacked Transistor Devices
App 20180342532 - MEHANDRU; Rishabh ; et al. | 2018-11-29 |
Backside Isolation For Integrated Circuit
App 20180331183 - LILAK; AARON D. ; et al. | 2018-11-15 |
Stacked Channel Structures For Mosfets
App 20180323195 - Mehandru; Rishabh ; et al. | 2018-11-08 |
Stacked Transistors
App 20180315838 - MORROW; Patrick ; et al. | 2018-11-01 |
Methods For Doping A Sub-fin Region Of A Semiconductor Structure By Backside Reveal And Associated Devices
App 20180248005 - LILAK; Aaron D. ; et al. | 2018-08-30 |
Semiconductor Device Contacts With Increased Contact Area
App 20180248011 - MEHANDRU; RISHABH ; et al. | 2018-08-30 |
Isolation Structures For An Integrated Circuit Element And Method Of Making Same
App 20180226478 - LILAK; Aaron D. ; et al. | 2018-08-09 |
Long Channel Mos Transistors For Low Leakage Applications On A Short Channel Cmos Chip
App 20180226492 - MEHANDRU; Rishabh ; et al. | 2018-08-09 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20180219075 - MORROW; Patrick ; et al. | 2018-08-02 |
Method, Device And System To Provide Capacitance For A Dynamic Random Access Memory Cell
App 20180219012 - LILAK; Aaron ; et al. | 2018-08-02 |
Hybrid Trigate And Nanowire Cmos Device Architecture
App 20180212023 - WEBER; Cory E. ; et al. | 2018-07-26 |
Deep Epi Enabled By Backside Reveal For Stress Enhancement & Contact
App 20180212057 - LILAK; Aaron D. ; et al. | 2018-07-26 |
Vertical Integration Scheme And Circuit Elements Architecture For Area Scaling Of Semiconductor Devices
App 20180204932 - MEHANDRU; Rishabh ; et al. | 2018-07-19 |
Semiconductor Nanowire Device Having Cavity Spacer And Method Of Fabricating Cavity Spacer For Semiconductor Nanowire Device
App 20180204955 - MEHANDRU; Rishabh ; et al. | 2018-07-19 |
Resistance Reduction In Transistors Having Epitaxially Grown Source/drain Regions
App 20180151732 - MEHANDRU; RISHABH ; et al. | 2018-05-31 |
Multi-height Finfet Device By Selective Oxidation
App 20180151702 - KIM; Seiyon ; et al. | 2018-05-31 |
Carbon-based Interface For Epitaxially Grown Source/drain Transistor Regions
App 20180151733 - GLASS; GLENN A. ; et al. | 2018-05-31 |
Methods Of Forming Low Interface Resistance Contacts And Structures Formed Thereby
App 20120068180 - Mehandru; Rishabh ; et al. | 2012-03-22 |
Wrap-around Contacts For Finfet And Tri-gate Devices
App 20110147840 - Cea; Stephen M. ; et al. | 2011-06-23 |
Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation
App 20110147804 - Mehandru; Rishabh ; et al. | 2011-06-23 |
Metal gate structures with recessed channel
Grant 7,943,992 - Sell , et al. May 17, 2 | 2011-05-17 |
Methods of forming low interface resistance contacts and structures formed thereby
App 20100109046 - Mehandru; Rishabh ; et al. | 2010-05-06 |
Methods of forming replacement metal gate structures with recessed channel
App 20090302398 - Sell; Bernhard ; et al. | 2009-12-10 |
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