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name:-0.01137900352478
name:-0.010973930358887
name:-0.00057697296142578
MEANEY; Patrick James Patent Filings

MEANEY; Patrick James

Patent Applications and Registrations

Patent applications and USPTO patent grants for MEANEY; Patrick James.The latest application filed is for "low latency availability in degraded redundant array of independent memory".

Company Profile
0.8.6
  • MEANEY; Patrick James - Poughkeepsie NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Low Latency Availability In Degraded Redundant Array Of Independent Memory
App 20210406126 - MEANEY; Patrick James ;   et al.
2021-12-30
Low latency availability in degraded redundant array of independent memory
Grant 11,200,119 - Meaney , et al. December 14, 2
2021-12-14
Refresh-hiding Memory System Staggered Refresh
App 20210216401 - MEANEY; PATRICK JAMES ;   et al.
2021-07-15
Low Latency Availability In Degraded Redundant Array Of Independent Memory
App 20210216400 - MEANEY; PATRICK JAMES ;   et al.
2021-07-15
Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy
Grant 7,987,400 - Berry , et al. July 26, 2
2011-07-26
Method of automating creation of a clock control distribution network in an integrated circuit floorplan
Grant 7,979,838 - Berry , et al. July 12, 2
2011-07-12
Method and apparatus for SRAM macro sparing in computer chips
Grant 7,702,972 - Bronson , et al. April 20, 2
2010-04-20
Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy
App 20090217115 - Berry; Christopher J. ;   et al.
2009-08-27
Method of Automating Creation of a Clock Control Distribution Network in an Integrated Circuit Floorplan
App 20090210843 - Berry; Christopher J. ;   et al.
2009-08-20
Method and Apparatus for SRAM Macro Sparing in Computer Chips
App 20090106607 - Bronson; Timothy Carl ;   et al.
2009-04-23
Method for supporting 11/2 cycle data paths via PLL based clock system
Grant 6,195,757 - McNamara , et al. February 27, 2
2001-02-27
Method for identifying SMP bus transfer errors
Grant 6,055,660 - Meaney April 25, 2
2000-04-25
Apparatus for identifying SMP bus transfer errors
Grant 5,784,383 - Meaney July 21, 1
1998-07-21
Reduced gate error detection and correction circuit
Grant 5,774,481 - Meaney , et al. June 30, 1
1998-06-30

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