loadpatents
name:-0.002551794052124
name:-0.017654895782471
name:-0.00043296813964844
McDonald; Edward A. Patent Filings

McDonald; Edward A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for McDonald; Edward A..The latest application filed is for "system and method for terminating lock-step sequences in a multiprocessor system".

Company Profile
0.17.1
  • McDonald; Edward A. - Baton Rouge LA
  • McDonald; Edward A. - Irvine CA
  • McDonald; Edward A. - Lexington SC
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System and method for terminating lock-step sequences in a multiprocessor system
Grant 6,754,787 - Miller , et al. June 22, 2
2004-06-22
System and method for terminating lock-step sequences in a multiprocessor system
App 20030070050 - Miller, Robert J. ;   et al.
2003-04-10
Method for preventing deadlock by suspending operation of processors, bridges, and devices
Grant 6,292,860 - Cochcroft, Jr. , et al. September 18, 2
2001-09-18
Microporous tubular prosthesis
Grant 6,120,535 - McDonald , et al. September 19, 2
2000-09-19
Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus
Grant 6,098,113 - Heil , et al. August 1, 2
2000-08-01
Self expandable tubular support
Grant 6,090,136 - McDonald , et al. July 18, 2
2000-07-18
Booting method for multi-processor computer
Grant 6,058,475 - McDonald , et al. May 2, 2
2000-05-02
Multiprocessor computing apparatus with optional coherency directory
Grant 6,012,127 - McDonald , et al. January 4, 2
2000-01-04
System for determining the average latency of pending pipelined or split transaction requests through using two counters and logic divider
Grant 5,919,268 - McDonald July 6, 1
1999-07-06
Method for distributing interprocessor interrupt requests via cache memory coherency mechanisms
Grant 5,765,195 - McDonald June 9, 1
1998-06-09
System and method of establishing error precedence in a computer system
Grant 5,758,065 - Reams , et al. May 26, 1
1998-05-26
Expandable microporous prosthesis
Grant 5,728,150 - McDonald , et al. March 17, 1
1998-03-17
Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses
Grant 5,701,422 - Kirkland, Jr. , et al. December 23, 1
1997-12-23
Two-piece, bifurcated intraluminal graft for repair of aneurysm
Grant 5,676,697 - McDonald October 14, 1
1997-10-14
Retry scheme for controlling transactions between two busses
Grant 5,418,914 - Heil , et al. May 23, 1
1995-05-23
Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces
Grant 5,359,715 - Heil , et al. October 25, 1
1994-10-25
Method and apparatus for decoding bus master arbitration levels to optimize memory transfers
Grant 5,327,540 - Heil , et al. July 5, 1
1994-07-05
Method and apparatus for transferring data within a computer system
Grant 5,269,005 - Heil , et al. December 7, 1
1993-12-07

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