McArdle; Timothy J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for McArdle; Timothy J..The latest application filed is for "faceted epitaxial source/drain regions".

Company Profile

14.38.34

McArdle; Timothy J. - Albuquerque NM
McArdle; Timothy J. - Ballston Lake NY
McArdle; Timothy J. - Mahopac NY
McArdle; Timothy J. - Hopewell Junction NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Faceted epitaxial source/drain regions Grant 10,756,184 - Mulfinger , et al. A	2020-08-25
Self-aligned sacrificial epitaxial capping for trench silicide Grant 10,741,556 - Mulfinger , et al. A	2020-08-11
Field-effect transistors with a grown silicon-germanium channel Grant 10,680,065 - Mulfinger , et al.	2020-06-09
Faceted Epitaxial Source/drain Regions App 20200144365 - MULFINGER; George R. ; et al.	2020-05-07
Field-effect Transistors With A Grown Silicon-germanium Channel App 20200044029 - Mulfinger; George R. ; et al.	2020-02-06
Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same Grant 10,396,078 - Holt , et al. A	2019-08-27
Methods of forming a gate-to-source/drain contact structure Grant 10,388,654 - Holt , et al. A	2019-08-20
Methods Of Forming A Gate-to-source/drain Contact Structure App 20190214387 - Holt; Judson R. ; et al.	2019-07-11
Post gate silicon germanium channel condensation and method for producing the same Grant 10,326,007 - Mulfinger , et al.	2019-06-18
Strain retention semiconductor member for channel SiGe layer of pFET Grant 10,236,343 - Triyoso , et al.	2019-03-19
Methods, apparatus and system for forming increased surface regions within EPI structures for improved trench silicide Grant 10,204,984 - Stoker , et al. Feb	2019-02-12
Post Gate Silicon Germanium Channel Condensation And Method For Producing The Same App 20190043967 - MULFINGER; George Robert ; et al.	2019-02-07
Methods, Apparatus And System For Forming Increased Surface Regions Within Epi Structures For Improved Trench Silicide App 20190043944 - Stoker; Matthew W. ; et al.	2019-02-07
Shaped Cavity For Epitaxial Semiconductor Growth App 20190027370 - Mulfinger; George R. ; et al.	2019-01-24
FinFETs with strained channels and reduced on state resistance Grant 10,134,876 - Krishnan , et al. November 20, 2	2018-11-20
Integrated Circuit Structure Including Laterally Recessed Source/drain Epitaxial Region And Method Of Forming Same App 20180286863 - Holt; Judson R. ; et al.	2018-10-04
FINFETs WITH STRAINED CHANNELS AND REDUCED ON STATE RESISTANCE App 20180286982 - KRISHNAN; Bharat V. ; et al.	2018-10-04
Self-aligned Sacrificial Epitaxial Capping For Trench Silicide App 20180233505 - MULFINGER; George R. ; et al.	2018-08-16
Post gate silicon germanium channel condensation and method for producing the same Grant 10,043,893 - Mulfinger , et al. August 7, 2	2018-08-07
Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same Grant 10,020,307 - Holt , et al. July 10, 2	2018-07-10
STRAIN RETENTION SEMICONDUCTOR MEMBER FOR CHANNEL SiGe LAYER OF pFET App 20180190768 - Triyoso; Dina H. ; et al.	2018-07-05
Methods of modulating the morphology of epitaxial semiconductor material Grant 9,953,873 - Chandra , et al. April 24, 2	2018-04-24
Recess liner for silicon germanium fin formation Grant 9,893,154 - McArdle , et al. February 13, 2	2018-02-13
Modulation Of The Morphology Of Epitaxial Semiconductor Material App 20170345719 - Chandra; Bhupesh ; et al.	2017-11-30
Self-aligned sacrificial epitaxial capping for trench silicide Grant 9,812,453 - Mulfinger , et al. November 7, 2	2017-11-07
Recess Liner For Silicon Germanium Fin Formation App 20170294515 - MCARDLE; Timothy J. ; et al.	2017-10-12
Carbon nanostructure device fabrication utilizing protect layers Grant 9,768,288 - Chu , et al. September 19, 2	2017-09-19
Buffer layer for modulating Vt across devices Grant 9,722,045 - Chandra , et al. August 1, 2	2017-08-01
Recess liner for silicon germanium fin formation Grant 9,698,226 - McArdle , et al. July 4, 2	2017-07-04
Carbon Nanostructure Device Fabrication Utilizing Protect Layers App 20170186881 - CHU; JACK O. ; et al.	2017-06-29
BUFFER LAYER FOR MODULATING Vt ACROSS DEVICES App 20170117387 - Chandra; Bhupesh ; et al.	2017-04-27
Methods Of Forming Replacement Fins Comprised Of Multiple Layers Of Different Semiconductor Materials App 20170033181 - McArdle; Timothy J. ; et al.	2017-02-02
Uniform junction formation in FinFETs Grant 9,466,616 - Harley , et al. October 11, 2	2016-10-11
Uniform Junction Formation In Finfets App 20160181285 - Harley; Eric C.T. ; et al.	2016-06-23
Epitaxially Grown Silicon Germanium Channel Finfet With Silicon Underlayer App 20160163707 - Cheng; Kangguo ; et al.	2016-06-09
Uniform junction formation in FinFETs Grant 9,318,608 - Harley , et al. April 19, 2	2016-04-19
Uniform Junction Formation In Finfets App 20160093740 - Harley; Eric C. T. ; et al.	2016-03-31
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels Grant 9,287,399 - Chandra , et al. March 15, 2	2016-03-15
Epitaxially grown silicon germanium channel FinFET with silicon underlayer Grant 9,287,264 - Cheng , et al. March 15, 2	2016-03-15
Graphene transistor with a sublithographic channel width Grant 9,236,477 - Chu , et al. January 12, 2	2016-01-12
Formation of a graphene layer on a large substrate Grant 9,236,250 - Chu , et al. January 12, 2	2016-01-12
Single-crystal Source-drain Merged By Polycrystalline Material App 20150270332 - Harley; Eric C. ; et al.	2015-09-24
Single crystal source-drain merged by polycrystalline material Grant 9,123,826 - Harley , et al. September 1, 2	2015-09-01
Graphene Transistor With A Sublithographic Channel Width App 20150236147 - Chu; Jack O. ; et al.	2015-08-20
Faceted Intrinsic Epitaxial Buffer Layer For Reducing Short Channel Effects While Maximizing Channel Stress Levels App 20150084096 - Chandra; Bhupesh ; et al.	2015-03-26
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels Grant 8,940,595 - Chandra , et al. January 27, 2	2015-01-27
Carbon Nanostructure Device Fabrication Utilizing Protect Layers App 20140374702 - CHU; JACK O. ; et al.	2014-12-25
Graphene growth on a non-hexagonal lattice Grant 8,877,340 - Chu , et al. November 4, 2	2014-11-04
Faceted Intrinsic Epitaxial Buffer Layer For Reducing Short Channel Effects While Maximizing Channel Stress Levels App 20140264558 - Chandra; Bhupesh ; et al.	2014-09-18
Carbon nanostructure device fabrication utilizing protect layers Grant 8,828,762 - Chu , et al. September 9, 2	2014-09-09
Carbon Nanostructure Device Fabrication Utilizing Protect Layers App 20140225193 - CHU; JACK O. ; et al.	2014-08-14
Semiconductor structure and circuit including ordered arrangement of graphene nanoribbons, and methods of forming same Grant 8,759,824 - Dimitrakopoulos , et al. June 24, 2	2014-06-24
Method for forming semiconductor chip with graphene based devices in an interconnect structure of the chip Grant 8,658,488 - Dimitrakopoulos , et al. February 25, 2	2014-02-25
Formation Of A Graphene Layer On A Large Substrate App 20130285014 - Chu; Jack O. ; et al.	2013-10-31
Formation of a graphene layer on a large substrate Grant 8,541,769 - Chu , et al. September 24, 2	2013-09-24
Semiconductor Chip With Graphene Based Devices In An Interconnect Structure Of The Chip App 20130203246 - Dimitrakopoulos; Christos D. ; et al.	2013-08-08
Graphene-containing semiconductor structures and devices on a silicon carbide substrate having a defined miscut angle Grant 8,476,617 - Dimitrakopoulos , et al. July 2, 2	2013-07-02
Semiconductor Structure And Circuit Including Ordered Arrangement Of Graphene Nanoribbons, And Methods Of Forming Same App 20130119350 - Dimitrakopoulos; Christos D. ; et al.	2013-05-16
Semiconductor chip with graphene based devices in an interconnect structure of the chip Grant 8,440,999 - Dimitrakopoulos , et al. May 14, 2	2013-05-14
Semiconductor structure and circuit including ordered arrangement of graphene nanoribbons, and methods of forming same Grant 8,354,296 - Dimitrakopoulos , et al. January 15, 2	2013-01-15
Graphene Growth On A Non-hexagonal Lattice App 20120319078 - Chu; Jack O. ; et al.	2012-12-20
Graphene-containing Semiconductor Structures And Devices On A Silicon Carbide Substrate Having A Defined Miscut Angle App 20120211723 - Dimitrakopoulos; Christos D. ; et al.	2012-08-23
Semiconductor Chip With Graphene Based Devices In An Interconnect Structure Of The Chip App 20120205626 - Dimitrakopoulos; Christos D. ; et al.	2012-08-16
Semiconductor Structure And Circuit Including Ordered Arrangment Of Graphene Nanoribbons, And Methods Of Forming Same App 20120181507 - Dimitrakopoulos; Christos D. ; et al.	2012-07-19
Epitaxial Growth Of Silicon Carbide On Sapphire App 20120112198 - Chu; Jack O. ; et al.	2012-05-10
Formation Of A Graphene Layer On A Large Substrate App 20120112164 - Chu; Jack O. ; et al.	2012-05-10
Graphene Growth On A Non-hexagonal Lattice App 20120028052 - Chu; Jack O. ; et al.	2012-02-02

Company Registrations

SEC

0001220148

MCARDLE TIMOTHY J

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.