loadpatents
name:-0.00054502487182617
name:-0.028928995132446
name:-0.00056600570678711
Mazure; Carlos A. Patent Filings

Mazure; Carlos A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mazure; Carlos A..The latest application filed is for "isolation collar nitride liner for dram process improvement".

Company Profile
0.24.0
  • Mazure; Carlos A. - Munich DE
  • Mazure; Carlos A. - Kirchseeon PE
  • Mazure; Carlos A. - Austin TX
  • Mazure; Carlos A. - Hopewell Junction NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Isolation collar nitride liner for DRAM process improvement
Grant 6,207,494 - Graimann , et al. March 27, 2
2001-03-27
Process for fabricating a DRAM trench capacitor
Grant 5,677,219 - Mazure , et al. October 14, 1
1997-10-14
Vertical transistor structure
Grant 5,627,395 - Witek , et al. May 6, 1
1997-05-06
Vertically stacked vertical transistors used to form vertical logic gate structures
Grant 5,612,563 - Fitch , et al. March 18, 1
1997-03-18
Vertically oriented DRAM structure
Grant 5,578,850 - Fitch , et al. November 26, 1
1996-11-26
Method for forming a vertically integrated dynamic memory cell
Grant 5,451,538 - Fitch , et al. September 19, 1
1995-09-19
Dynamic memory device having a vertical transistor
Grant 5,414,289 - Fitch , et al. May 9, 1
1995-05-09
Vertical transistor having an underlying gate electrode contact
Grant 5,414,288 - Fitch , et al. May 9, 1
1995-05-09
Vertically formed semiconductor random access memory device
Grant 5,398,200 - Mazure , et al. March 14, 1
1995-03-14
Method for forming a compact transistor structure
Grant 5,393,681 - Witek , et al. February 28, 1
1995-02-28
Method for forming a transistor having a dynamic connection between a substrate and a channel region
Grant 5,340,754 - Witek , et al. August 23, 1
1994-08-23
Method of formation of vertical transistor
Grant 5,324,673 - Fitch , et al. June 28, 1
1994-06-28
Field effect transistor having a gate dielectric with variable thickness
Grant 5,314,834 - Mazure , et al. May 24, 1
1994-05-24
Semiconductor memory device and method of formation
Grant 5,308,782 - Mazure , et al. May 3, 1
1994-05-03
Temperature controlled process for the epitaxial growth of a film of material
Grant 5,308,788 - Fitch , et al. May 3, 1
1994-05-03
Method of formation of transistor and logic gates
Grant 5,308,778 - Fitch , et al. May 3, 1
1994-05-03
Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell
Grant 5,256,588 - Witek , et al. October 26, 1
1993-10-26
Transistor useful for further vertical integration and method of formation
Grant 5,252,849 - Fitch , et al. October 12, 1
1993-10-12
Method for forming pitch independent contacts and a semiconductor device having the same
Grant 5,219,793 - Cooper , et al. June 15, 1
1993-06-15
Method for forming a grown bipolar electrode contact using a sidewall seed
Grant 5,213,989 - Fitch , et al. May 25, 1
1993-05-25
ITLDD transistor having a variable work function
Grant 5,210,435 - Roth , et al. May 11, 1
1993-05-11
Method for forming a raised vertical transistor
Grant 5,208,172 - Fitch , et al. May 4, 1
1993-05-04
Method for forming a bipolar transistor structure
Grant 5,198,375 - Hayden , et al. March 30, 1
1993-03-30
ITLDD transistor having variable work function and method for fabricating the same
Grant 5,061,647 - Roth , et al. October 29, 1
1991-10-29

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