Maziasz; Robert L.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Maziasz; Robert L..The latest application filed is for "synthesis of complex cells".
- Maziasz; Robert L. - Austin TX US
| Patent | Date |
|---|---|
| Method and control device for circuit layout migration Grant 9,928,331 - Rozenfeld , et al. March 27, 2 | 2018-03-27 |
| Synthesis of complex cells Grant 9,293,450 - Maziasz March 22, 2 | 2016-03-22 |
| Synthesis Of Complex Cells App 20160027768 - Maziasz; Robert L. | 2016-01-28 |
| Method And Control Device For Circuit Layout Migration App 20150356224 - ROZENFELD; VLADIMIR PAVLOVICH ; et al. | 2015-12-10 |
| Cell routability prioritization Grant 8,978,004 - Maziasz , et al. March 10, 2 | 2015-03-10 |
| Double patterning aware routing without stitching Grant 8,762,898 - Maziasz June 24, 2 | 2014-06-24 |
| Transistor-level layout synthesis Grant 8,726,218 - Maziasz , et al. May 13, 2 | 2014-05-13 |
| Reducing leakage in standard cells Grant 8,612,915 - Sundareswaran , et al. December 17, 2 | 2013-12-17 |
| Cell Routability Prioritization App 20130212549 - Maziasz; Robert L. ; et al. | 2013-08-15 |
| Transistor-level Layout Synthesis App 20120159412 - Maziasz; Robert L. ; et al. | 2012-06-21 |
| Method of area compaction for integrated circuit layout design Grant 7,904,869 - Yu , et al. March 8, 2 | 2011-03-08 |
| System and method for electromigration tolerant cell synthesis Grant 7,721,245 - Maziasz , et al. May 18, 2 | 2010-05-18 |
| Method Of Area Compaction For Integrated Circuit Layout Design App 20090158229 - Yu; Kathleen C. ; et al. | 2009-06-18 |
| System and method for electromigration tolerant cell synthesis App 20080092100 - Maziasz; Robert L. ; et al. | 2008-04-17 |
| Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors Grant 6,209,123 - Maziasz , et al. March 27, 2 | 2001-03-27 |
| Method for optimizing contact pin placement in an integrated circuit Grant 6,075,934 - Chiluvuri , et al. June 13, 2 | 2000-06-13 |
| Method of routing an integrated circuit Grant 6,006,024 - Guruswamy , et al. December 21, 1 | 1999-12-21 |
| Automatic layout standard cell routing Grant 5,987,086 - Raman , et al. November 16, 1 | 1999-11-16 |
| Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method Grant 5,689,432 - Blaauw , et al. November 18, 1 | 1997-11-18 |
| Method and apparatus for designing an integrated circuit Grant 5,666,288 - Jones , et al. September 9, 1 | 1997-09-09 |
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