May; Cathy

Patent Applications and Registrations

Patent applications and USPTO patent grants for May; Cathy.The latest application filed is for "translation load instruction".

Company Profile

7.45.46

May; Cathy - Ossining NY
May; Cathy - Yorktown NY
May; Cathy - Millwood NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Translation load instruction with access protection Grant 11,226,902 - Williams , et al. January 18, 2	2022-01-18
Translation Load Instruction App 20210096859 - WILLIAMS; DEREK E. ; et al.	2021-04-01
Interruptible translation entry invalidation in a multithreaded data processing system Grant 10,817,434 - Williams , et al. October 27, 2	2020-10-27
Interruptible Translation Entry Invalidation In A Multithreaded Data Processing System App 20200201780 - WILLIAMS; DEREK E. ; et al.	2020-06-25
Efficient enforcement of barriers with respect to memory move sequences Grant 10,613,792 - Frey , et al.	2020-04-07
Hardware based isolation for secure execution of virtual machines Grant 10,387,686 - Boivie , et al. A	2019-08-20
Hardware Based Isolation For Secure Execution Of Virtual Machines App 20190034666 - Boivie; Richard H. ; et al.	2019-01-31
Efficient Enforcement Of Barriers With Respect To Memory Move Sequences App 20180373436 - FREY; BRADLY G. ; et al.	2018-12-27
Memory move instruction sequence including a stream of copy-type and paste-type instructions Grant 10,152,322 - Frey , et al. Dec	2018-12-11
Efficient enforcement of barriers with respect to memory move sequences Grant 10,067,713 - Frey , et al. September 4, 2	2018-09-04
Efficient Enforcement Of Barriers With Respect To Memory Move Sequences App 20180052606 - FREY; BRADLY G. ; et al.	2018-02-22
Memory Move Instruction Sequence Including A Stream Of Copy-type And Paste-type Instructions App 20180052687 - FREY; BRADLY G. ; et al.	2018-02-22
Translation entry invalidation in a multithreaded data processing system Grant 9,785,557 - Frey , et al. October 10, 2	2017-10-10
Translation entry invalidation in a multithreaded data processing system Grant 9,772,945 - Frey , et al. September 26, 2	2017-09-26
Transactional memory system supporting unbroken suspended execution Grant 9,626,187 - Cain, III , et al. April 18, 2	2017-04-18
Determining failure context in hardware transactional memories Grant 9,626,256 - Cain , et al. April 18, 2	2017-04-18
Interaction of transactional storage accesses with other atomic semantics Grant 9,430,166 - Frey , et al. August 30, 2	2016-08-30
Rewind only transactions in a data processing system supporting transactional storage accesses Grant 9,396,115 - Blainey , et al. July 19, 2	2016-07-19
Transaction check instruction for memory transactions Grant 9,367,264 - Frey , et al. June 14, 2	2016-06-14
Transaction check instruction for memory transactions Grant 9,367,263 - Frey , et al. June 14, 2	2016-06-14
Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses Grant 9,342,454 - Frey , et al. May 17, 2	2016-05-17
Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories Grant 9,268,598 - Blainey , et al. February 23, 2	2016-02-23
Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories Grant 9,268,599 - Blainey , et al. February 23, 2	2016-02-23
Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses Grant 9,244,846 - Frey , et al. January 26, 2	2016-01-26
Conditional transaction abort and precise abort handling Grant 9,081,607 - Blainey , et al. July 14, 2	2015-07-14
Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition Grant 9,047,079 - Bruce , et al. June 2, 2	2015-06-02
Multiple page size segment encoding Grant 8,745,307 - Chadha , et al. June 3, 2	2014-06-03
Method And Apparatus For Conditional Transaction Abort And Precise Abort Handling App 20140115590 - Blainey; Robert J ; et al.	2014-04-24
Method And Apparatus For Recording And Profiling Transaction Failure Source Addresses In Hardware Transactional Memories App 20140081936 - Blainey; Robert J. ; et al.	2014-03-20
Method And Apparatus For Determining Failure Context In Hardware Transactional Memories App 20140075132 - Cain; Harold W. ; et al.	2014-03-13
Method And Apparatus For Recording And Profiling Transaction Failure Source Addresses In Hardware Transactional Memories App 20140075441 - Blainey; Robert J. ; et al.	2014-03-13
Method And Apparatus For Determining Failure Context In Hardware Transactional Memories App 20140075131 - Cain; Harold W. ; et al.	2014-03-13
Interaction Of Transactional Storage Accesses With Other Atomic Semantics App 20140047205 - FREY; BRADLY G. ; et al.	2014-02-13
Transaction Check Instruction For Memory Transactions App 20140047195 - FREY; Bradly G. ; et al.	2014-02-13
Transaction Check Instruction For Memory Transactions App 20140047196 - FREY; BRADLY G. ; et al.	2014-02-13
Nested Rewind Only And Non Rewind Only Transactions In A Data Processing System Supporting Transactional Storage Accesses App 20140040557 - FREY; BRADLY G. ; et al.	2014-02-06
Rewind Only Transactions In A Data Processing System Supporting Transactional Storage Accesses App 20140040551 - BLAINEY; ROBERT J. ; et al.	2014-02-06
Ensuring Causality Of Transactional Storage Accesses Interacting With Non-transactional Storage Accesses App 20140013060 - Frey; Bradly G. ; et al.	2014-01-09
Ensuring Causality Of Transactional Storage Accesses Interacting With Non-transactional Storage Accesses App 20140013055 - Frey; Bradly G. ; et al.	2014-01-09
Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition Grant 8,615,644 - Bruce , et al. December 24, 2	2013-12-24
Transactional memory preemption mechanism Grant 8,544,022 - Arndt , et al. September 24, 2	2013-09-24
Transactional memory preemption mechanism Grant 8,424,015 - Arndt , et al. April 16, 2	2013-04-16
Transactional Memory Preemption Mechanism App 20120246658 - Arndt; Richard L. ; et al.	2012-09-27
Hardware Thread Disable With Status Indicating Safe Shared Resource Condition App 20120185678 - Bruce; Becky ; et al.	2012-07-19
Specifying an access hint for prefetching limited use data in a cache hierarchy Grant 8,176,254 - Frey , et al. May 8, 2	2012-05-08
Transactional Memory Preemption Mechanism App 20120084477 - Arndt; Richard L. ; et al.	2012-04-05
Specifying an access hint for prefetching partial cache block data in a cache hierarchy Grant 8,140,759 - Frey , et al. March 20, 2	2012-03-20
Transactional Memory System Supporting Unbroken Suspended Execution App 20110296148 - Cain, III; Harold W. ; et al.	2011-12-01
Multiple Page Size Segment Encoding App 20110283040 - Chadha; Sundeep ; et al.	2011-11-17
Hypervisor-enforced isolation of entities within a single logical partition's virtual address space Grant 8,010,763 - Armstrong , et al. August 30, 2	2011-08-30
Hardware Thread Disable With Status Indicating Safe Shared Resource Condition App 20110208949 - Bruce; Becky ; et al.	2011-08-25
Mechanism for avoiding check stops in speculative accesses while operating in real mode Grant 7,949,859 - Kalla , et al. May 24, 2	2011-05-24
Data stream prefetching in a microprocessor Grant 7,904,661 - Fluhr , et al. March 8, 2	2011-03-08
Selectively invalidating entries in an address translation cache Grant 7,822,942 - Corrigan , et al. October 26, 2	2010-10-26
Specifying An Access Hint For Prefetching Partial Cache Block Data In A Cache Hierarchy App 20100268886 - Frey; Bradly George ; et al.	2010-10-21
Specifying An Access Hint For Prefetching Limited Use Data In A Cache Hierarchy App 20100268885 - Frey; Bradly G. ; et al.	2010-10-21
Method and apparatus for selecting the architecture level to which a processor appears to conform Grant 7,802,252 - Armstrong , et al. September 21, 2	2010-09-21
Mechanism for Avoiding Check Stops in Speculative Accesses While Operating in Real Mode App 20090193233 - Kalla; Ronald N. ; et al.	2009-07-30
Hypervisor-enforced Isolation Of Entities Within A Single Logical Partition's Virtual Address Space App 20090037682 - ARMSTRONG; William J. ; et al.	2009-02-05
Selectively Invalidating Entries In An Address Translation Cache App 20080168254 - Corrigan; Michael J. ; et al.	2008-07-10
Method and Apparatus For Selecting the Architecture Level to Which a Processor Appears to Conform App 20080168258 - Armstrong; William J. ; et al.	2008-07-10
Apparatus and method for selectively invalidating entries in an address translation cache Grant 7,389,400 - Corrigan , et al. June 17, 2	2008-06-17
Mechanism for avoiding check stops in speculative accesses while operating in real mode Grant 7,370,177 - Kalla , et al. May 6, 2	2008-05-06
Data stream prefetching in a microprocessor App 20080091922 - Fluhr; Eric Jason ; et al.	2008-04-17
Data stream prefetching in a microprocessor Grant 7,350,029 - Fluhr , et al. March 25, 2	2008-03-25
System and Method for Providing a Mediated External Exception Extension for a Microprocessor App 20080034193 - Day; Michael N. ; et al.	2008-02-07
Apparatus and method for selectively invalidating entries in an address translation cache App 20070143565 - Corrigan; Michael J. ; et al.	2007-06-21
Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor Grant 7,143,267 - Fluhr , et al. November 28, 2	2006-11-28
Data stream prefetching in a microprocessor App 20060179239 - Fluhr; Eric Jason ; et al.	2006-08-10
Method of effective to real address translation for a multi-threaded microprocessor App 20050182912 - DeMent, Jonathan James ; et al.	2005-08-18
Translation look-aside buffer sharing among logical partitions App 20050027960 - DeMent, Jonathan James ; et al.	2005-02-03
Limiting concurrent modification and execution of instructions to a particular type to avoid unexpected results Grant 6,823,445 - May , et al. November 23, 2	2004-11-23
Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register App 20040215892 - Fluhr, Eric J. ; et al.	2004-10-28
Mechanism for avoiding check stops in speculative accesses while operating in real mode App 20040216001 - Kalla, Ronald N. ; et al.	2004-10-28
Concurrent modification and execution of instructions App 20030028757 - May, Cathy ; et al.	2003-02-06
Data processing system for processing vector data and method therefor Grant 6,202,130 - Scales, III , et al. March 13, 2	2001-03-13

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