| Patent | Date |
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Integrating diverse transistors on the same wafer
Grant 8,450,199 - Piazza , et al. May 28, 2 | 2013-05-28 |
Process for manufacturing a memory device integrated on a semiconductor substrate and comprising nanocrystal memory cells and CMOS transistors
Grant 7,910,978 - Maurelli March 22, 2 | 2011-03-22 |
Integrating Diverse Transistors On The Same Wafer
App 20100155852 - Piazza; Fausto ; et al. | 2010-06-24 |
Process For Manufacturing A Memory Device Integrated On A Semiconductor Substrate And Comprising Nanocristal Memory Cells And Cmos Transistors
App 20080296658 - Maurelli; Alfonso | 2008-12-04 |
Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure
Grant 7,410,872 - Maurelli August 12, 2 | 2008-08-12 |
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit
Grant 7,320,904 - Cappelletti , et al. January 22, 2 | 2008-01-22 |
Manufacturing Method For Non-active Electrically Structures Of An Integrated Electronic Circuit Formed On A Semiconductor Substrate And Corresponding Electronic Circuit
App 20070287290 - Maurelli; Alfonso ; et al. | 2007-12-13 |
Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture
Grant 7,304,485 - Cappelletti , et al. December 4, 2 | 2007-12-04 |
Sealing Method For Electronic Devices Formed On A Common Semiconductor Substrate And Corresponding Circuit Structure
App 20070026610 - Camerlenghi; Emilio ; et al. | 2007-02-01 |
Sealing Method For Electronic Devices Formed On A Common Semiconductor Substrate And Corresponding Circuit Structure
App 20070026576 - Maurelli; Alfonso | 2007-02-01 |
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit
App 20060189136 - Cappelletti; Paolo Giuseppe ; et al. | 2006-08-24 |
Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure
Grant 7,078,294 - Camerlenghi , et al. July 18, 2 | 2006-07-18 |
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit
Grant 7,001,800 - Cappelletti , et al. February 21, 2 | 2006-02-21 |
Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure
App 20050112905 - Camerlenghi, Emilio ; et al. | 2005-05-26 |
Electrically erasable and programmable non-volatile memory cell
Grant 6,876,033 - Cappelletti , et al. April 5, 2 | 2005-04-05 |
Manufacturing method for non-active electrically structures in order to optimize the definition of active electrically structures in an electronic circuit integrated on a semiconductor substrate and corresponding circuit
App 20050032278 - Cappelletti, Paolo Giuseppe ; et al. | 2005-02-10 |
Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture
App 20040268275 - Cappelletti, Paolo ; et al. | 2004-12-30 |
Electrically erasable and programmable non-volatile memory cell
App 20040061168 - Cappelletti, Paolo ; et al. | 2004-04-01 |
Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry
Grant 6,713,347 - Cappelletti , et al. March 30, 2 | 2004-03-30 |
Method of forming low-resistivity connections in non-volatile memories
Grant 6,686,241 - Ati , et al. February 3, 2 | 2004-02-03 |
Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip
Grant 6,627,928 - Peschiaroli , et al. September 30, 2 | 2003-09-30 |
Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip
App 20030032244 - Peschiaroli, Daniela ; et al. | 2003-02-13 |
Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip
Grant 6,482,698 - Peschiaroli , et al. November 19, 2 | 2002-11-19 |
Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry
App 20020140047 - Cappelletti, Paolo Giuseppe ; et al. | 2002-10-03 |
Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device
App 20020119616 - Baldi, Livio ; et al. | 2002-08-29 |
Non-volatile memory cell with a single level of polysilicon, in particular of the flash EEPROM type, and method for manufacturing the same
Grant 6,410,389 - Cappelletti , et al. June 25, 2 | 2002-06-25 |
Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry
Grant 6,410,387 - Cappelletti , et al. June 25, 2 | 2002-06-25 |
Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device
Grant 6,399,442 - Baldi , et al. June 4, 2 | 2002-06-04 |
Method Of Manufacturing An Integrated Semiconductor Device Having A Nonvolatile Floating Gate Memiry, And Related Integrated Device
App 20020045316 - BALDI, LIVIO ; et al. | 2002-04-18 |
Method of fabrication of a no-field MOS transistor
Grant 6,350,637 - Maurelli , et al. February 26, 2 | 2002-02-26 |
Manufacturing process for the integration in a semiconductor chip of an integrated circuit including a high-density integrated circuit components portion and a high-performance logic integrated circuit components portion
App 20020008222 - Maurelli, Alfonso | 2002-01-24 |
Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip
App 20010049166 - Peschiaroli, Daniela ; et al. | 2001-12-06 |
Method of forming low-resistivity connections in non-volatile memories
App 20010049176 - Ati, Massimo ; et al. | 2001-12-06 |
Process for obtaining an N-channel single polysilicon level EPROM cell and cell obtained with said process
Grant 5,307,312 - Maurelli , et al. April 26, 1 | 1994-04-26 |
Method of manufacturing integrated circuits having electronic components of two different types each having pairs of electrodes obtained from the same polycrystalline silicon layers and separated by different dielectric materials
Grant 5,075,246 - Re , et al. December 24, 1 | 1991-12-24 |
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