Matulik; Eric

Patent Applications and Registrations

Patent applications and USPTO patent grants for Matulik; Eric.The latest application filed is for "access to dram through a reuse of pins".

Company Profile

4.11.14

Matulik; Eric - Meyreuil FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Safety enhancement for memory controllers Grant 10,747,611 - Vergnes , et al. A	2020-08-18
Access to DRAM through a reuse of pins Grant 10,620,881 - Matulik , et al.	2020-04-14
Access to DRAM Through a Reuse of Pins App 20190324686 - Matulik; Eric ; et al.	2019-10-24
Safety Enhancement for Memory Controllers App 20190220346 - Vergnes; Alain ; et al.	2019-07-18
Proactive Quality Of Service In Multi-matrix System Bus App 20170017593 - Lunadier; Franck ; et al.	2017-01-19
Proactive quality of service in multi-matrix system bus Grant 9,372,818 - Lunadier , et al. June 21, 2	2016-06-21
Proactive Quality Of Service In Multi-matrix System Bus App 20140281081 - Lunadier; Franck ; et al.	2014-09-18
Apparatus to improve bandwidth for circuits having multiple memory controllers Grant 8,468,281 - Matulik June 18, 2	2013-06-18
Read-data stage circuitry for DDR-SDRAM memory controller Grant 7,739,539 - Vergnes , et al. June 15, 2	2010-06-15
Clock circuitry for DDR-SDRAM memory controller Grant 7,679,987 - Vergnes , et al. March 16, 2	2010-03-16
Circuits To Delay Signals From A Memory Device App 20090238016 - Matulik; Eric ; et al.	2009-09-24
Apparatus To Improve Bandwidth For Circuits Having Multiple Memory Controllers App 20090216926 - Matulik; Eric	2009-08-27
Circuits to delay a signal from a memory device Grant 7,539,078 - Matulik , et al. May 26, 2	2009-05-26
Circuits To Delay A Signal From A Memory Device App 20090077409 - Matulik; Eric ; et al.	2009-03-19
Clock Circuitry For Ddr-sdram Memory Controller App 20090010083 - Vergnes; Alain ; et al.	2009-01-08
Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction Grant 7,433,262 - Vergnes , et al. October 7, 2	2008-10-07
Clock circuitry for DDR-SDRAM memory controller Grant 7,423,928 - Vergnes , et al. September 9, 2	2008-09-09
Clock Circuitry For Ddr-sdram Memory Controller App 20080181046 - Vergnes; Alain ; et al.	2008-07-31
Circuits To Delay A Signal From Ddr-sdram Memory Device Including An Automatic Phase Error Correction App 20080123445 - Vergnes; Alain ; et al.	2008-05-29
Read-data stage circuitry for DDR-SDRAM memory controller App 20080091903 - Vergnes; Alain ; et al.	2008-04-17
Method and apparatus for reducing system inactivity during time data float delay and external memory write Grant 7,269,704 - Matulik , et al. September 11, 2	2007-09-11
Apparatus to improve bandwidth for circuits having multiple memory controllers App 20060236007 - Matulik; Eric	2006-10-19
Method and apparatus for reducing system inactivity during time data float delay and external memory write App 20060224848 - Matulik; Eric ; et al.	2006-10-05

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