loadpatents
name:-0.0092010498046875
name:-0.03173303604126
name:-0.00060486793518066
Matsuo; Masahito Patent Filings

Matsuo; Masahito

Patent Applications and Registrations

Patent applications and USPTO patent grants for Matsuo; Masahito.The latest application filed is for "data processor for modifying and executing operation of instruction code".

Company Profile
0.25.7
  • Matsuo; Masahito - Hyogo JP
  • Matsuo; Masahito - Tokyo JP
  • Matsuo; Masahito - Hyogo-ken JP
  • Matsuo; Masahito - Itami JP
  • Matsuo; Masahito - Itamishi JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Data processor for modifying and executing operation of instruction code according to the indication of other instruction code
Grant 7,487,338 - Matsuo February 3, 2
2009-02-03
Data processor for modifying and executing operation of instruction code
App 20080082800 - Matsuo; Masahito
2008-04-03
Data processor
App 20070174596 - Matsuo; Masahito
2007-07-26
Data processor speeding up repeat processing by inhibiting remaining instructions after a break in a repeat block
Grant 7,010,677 - Matsuo March 7, 2
2006-03-07
Data processor
App 20050283589 - Matsuo, Masahito
2005-12-22
Data processor assigning the same operation code to multiple operations
Grant 6,925,548 - Matsuo August 2, 2
2005-08-02
Data processor and method of processing data
Grant RE38,679 - Matsuo , et al. December 28, 2
2004-12-28
Data processor for modifying and executing operation of instruction code
App 20040015680 - Matsuo, Masahito
2004-01-22
Data processor
App 20030061471 - Matsuo, Masahito
2003-03-27
Data processor
Grant 6,484,253 - Matsuo November 19, 2
2002-11-19
Data processor
App 20020133692 - Matsuo, Masahito
2002-09-19
Data processor assigning the same operation code to multiple operations
App 20020120830 - Matsuo, Masahito
2002-08-29
Data processor capable of executing two instructions having operand interference at high speed in parallel
Grant 6,178,492 - Matsuo January 23, 2
2001-01-23
Data processor
Grant 6,151,673 - Matsuo , et al. November 21, 2
2000-11-21
Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel
Grant 6,131,158 - Matsuo , et al. October 10, 2
2000-10-10
Data processor
Grant 6,112,289 - Matsuo August 29, 2
2000-08-29
Circular buffer with two different step sizes
Grant 5,924,114 - Maruyama , et al. July 13, 1
1999-07-13
Data processor and method of processing data
Grant 5,901,301 - Matsuo , et al. May 4, 1
1999-05-04
Data processor with branch target address generating unit
Grant 5,848,268 - Matsuo December 8, 1
1998-12-08
Data processing system capable of execution of plural instructions in parallel
Grant 5,812,809 - Matsuo , et al. September 22, 1
1998-09-22
Data processing system capable of execution of plural instructions in parallel
Grant 5,615,349 - Matsuo , et al. March 25, 1
1997-03-25
Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction
Grant 5,485,587 - Matsuo , et al. January 16, 1
1996-01-16
Data processor capable of execution of plural instructions in parallel
Grant 5,461,715 - Matsuo , et al. October 24, 1
1995-10-24
Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address
Grant 5,355,459 - Matsuo , et al. October 11, 1
1994-10-11
System for processing parameters in instructions of different format to execute the instructions using same microinstructions
Grant 5,321,821 - Itomitsu , et al. June 14, 1
1994-06-14
System having status update controller for determining which one of parallel operation results of execution units is allowed to set conditions of shared processor status word
Grant 5,313,644 - Matsuo , et al. May 17, 1
1994-05-17
System for selecting control parameter for microinstruction execution unit using parameters and parameter selection signal decoded from instruction
Grant 5,220,656 - Itomitsu , et al. June 15, 1
1993-06-15
Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
Grant 5,193,205 - Matsuo , et al. March 9, 1
1993-03-09
Computer with instruction prefetch queue retreat unit
Grant 4,974,154 - Matsuo November 27, 1
1990-11-27
Preceding instruction address based branch prediction in a pipelined processor
Grant 4,858,104 - Matsuo , et al. August 15, 1
1989-08-15
Pipelined computer
Grant 4,847,753 - Matsuo , et al. July 11, 1
1989-07-11
Instruction fetching in data processing apparatus
Grant 4,796,175 - Matsuo , et al. January 3, 1
1989-01-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed