Matlock; Dyer A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Matlock; Dyer A..The latest application filed is for "process for forming twin well cmos integrated circuits".

Company Profile

0.8.0

Matlock; Dyer A. - Melbourne FL

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Patent Activity

Patent	Date
Process for forming twin well CMOS integrated circuits Grant 5,429,958 - Matlock July 4, 1	1995-07-04
Process for forming extremely thin edge-connectable integrated circuit structure Grant 5,185,292 - VanVonno , et al. February 9, 1	1993-02-09
Process for forming extremely thin integrated circuit dice Grant 5,071,792 - VanVonno , et al. December 10, 1	1991-12-10
Technique for elimination of polysilicon stringers in direct moat field oxide structure Grant 4,908,683 - Matlock , et al. March 13, 1	1990-03-13
CMOS device having reduced spacing between N and P channel Grant 4,829,359 - O , et al. May 9, 1	1989-05-09
Method for forming planarized interconnect level using selective deposition and ion implantation Grant 4,814,285 - Matlock , et al. March 21, 1	1989-03-21
Method of ensuring adhesion of chemically vapor deposited oxide to gold integrated circuit interconnect lines Grant 4,713,260 - Roberts , et al. December 15, 1	1987-12-15
Electrodeposition of submicrometer metallic interconnect for integrated circuits Grant 4,624,749 - Black , et al. November 25, 1	1986-11-25

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