Matick; Richard E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Matick; Richard E..The latest application filed is for "edram hierarchical differential sense amp".

Company Profile

0.18.9

Matick; Richard E. - Cortlandt Manor NY
Matick; Richard E. - Cortland NY
Matick; Richard E. - Peekskill NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
eDRAM hierarchical differential sense AMP Grant 7,821,858 - Matick , et al. October 26, 2	2010-10-26
Hierarchical 2T-DRAM with self-timed sensing Grant 7,709,299 - Matick , et al. May 4, 2	2010-05-04
eDRAM Hierarchical Differential Sense AMP App 20090080230 - Matick; Richard E. ; et al.	2009-03-26
Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line Grant 7,499,312 - Matick , et al. March 3, 2	2009-03-03
Hierarchical six-transistor SRAM Grant 7,471,546 - Matick , et al. December 30, 2	2008-12-30
Hierarchical 2t-dram With Self-timed Sensing App 20080308941 - Matick; Richard E. ; et al.	2008-12-18
eDRAM hierarchical differential sense amp Grant 7,460,387 - Matick , et al. December 2, 2	2008-12-02
Hierarchical 2T-DRAM with self-timed sensing Grant 7,460,423 - Matick , et al. December 2, 2	2008-12-02
Systems And Methods For A Dram Concurrent Refresh Engine With Processor Interface App 20080270683 - Barth; John E. ; et al.	2008-10-30
Hierarchical 2T-DRAM with Self-Timed Sensing App 20080165560 - Matick; Richard E. ; et al.	2008-07-10
Fast, Stable, Sram Cell Using Seven Devices And Hierarchical Bit/sense Line App 20080165562 - Matick; Richard E. ; et al.	2008-07-10
Hierarchical Six-transistor Sram App 20080165561 - Matick; Richard E. ; et al.	2008-07-10
eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP App 20080165601 - Matick; Richard E. ; et al.	2008-07-10
Dram Hierarchical Data Path App 20080016277 - Matick; Richard E. ; et al.	2008-01-17
DRAM hierarchical data path Grant 7,289,369 - Matick , et al. October 30, 2	2007-10-30
DRAM hierarchical data path App 20060233024 - Matick; Richard E. ; et al.	2006-10-19
Mapping and logic for combining L1 and L2 directories and/or arrays Grant 6,981,096 - Matick , et al. December 27, 2	2005-12-27
Bit line switch array for electronic computer memory Grant 5,388,072 - Matick , et al. February 7, 1	1995-02-07
Functional cache memory chip architecture for improved cache access Grant 4,905,188 - Chuang , et al. February 27, 1	1990-02-27
Circuits for accessing a variable width data bus with a variable width data field Grant 4,667,305 - Dill , et al. May 19, 1	1987-05-19
Display architecture having variable data width Grant 4,663,729 - Matick , et al. May 5, 1	1987-05-05
Dynamic row buffer circuit for DRAM Grant 4,649,516 - Chung , et al. March 10, 1	1987-03-10
Communicating random access memory Grant 4,616,310 - Dill , et al. October 7, 1	1986-10-07
Data buffer having separate lock bit storage array Grant 4,589,092 - Matick May 13, 1	1986-05-13
Distributed, on-chip cache Grant 4,577,293 - Matick , et al. March 18, 1	1986-03-18
Random access memory having a second input/output port Grant 4,541,075 - Dill , et al. September 10, 1	1985-09-10
High speed high density, multi-port random access memory cell Grant 4,287,575 - Eardley , et al. September 1, 1	1981-09-01

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