loadpatents
name:-0.025268077850342
name:-0.040568113327026
name:-0.048067808151245
Mathews; Gregory S. Patent Filings

Mathews; Gregory S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mathews; Gregory S..The latest application filed is for "ordering memory requests based on access efficiency".

Company Profile
17.35.20
  • Mathews; Gregory S. - Saratoga CA
  • Mathews; Gregory S. - Santa Clara CA
  • Mathews; Gregory S. - Boca Raton FL
  • Mathews; Gregory S. - Cupertino CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Ordering memory requests based on access efficiency
Grant 11,403,037 - Keil , et al. August 2, 2
2022-08-02
Write/read turn techniques based on latency tolerance
Grant 11,221,798 - Mathews , et al. January 11, 2
2022-01-11
Memory access scheduling using category arbitration
Grant 10,901,617 - Mathews , et al. January 26, 2
2021-01-26
Memory access quality-of-service reallocation
Grant 10,838,884 - Magudilu Vijavaraj , et al. November 17, 2
2020-11-17
Memory access scheduling using a linked list
Grant 10,817,219 - Nukala , et al. October 27, 2
2020-10-27
Ordering Memory Requests Based On Access Efficiency
App 20200301615 - Keil; Shane J. ;   et al.
2020-09-24
Memory request management system
Grant 10,783,104 - Mathews , et al. Sept
2020-09-22
System and method for performing per-bank memory refresh
Grant 10,777,252 - Fu , et al. Sept
2020-09-15
Ordering memory requests based on access efficiency
Grant 10,678,478 - Keil , et al.
2020-06-09
Write/read Turn Techniques Based On Latency Tolerance
App 20200159463 - Mathews; Gregory S. ;   et al.
2020-05-21
Memory Request Management System
App 20200133905 - Mathews; Gregory S. ;   et al.
2020-04-30
System and method for communication link management in a credit-based system
Grant 10,621,115 - Mathews , et al.
2020-04-14
Memory Access Scheduling Using A Linked List
App 20200081652 - Nukala; Lakshmi Narasimha Murthy ;   et al.
2020-03-12
Memory Access Scheduling Using Category Arbitration
App 20200081622 - Mathews; Gregory S. ;   et al.
2020-03-12
System and Method for Performing Per-Bank Memory Refresh
App 20200066328 - Fu; Peter ;   et al.
2020-02-27
Ordering Memory Requests Based On Access Efficiency
App 20200065028 - Keil; Shane J. ;   et al.
2020-02-27
Memory Arbitration Techniques Based On Latency Tolerance
App 20200057579 - Mathews; Gregory S. ;   et al.
2020-02-20
Memory arbitration techniques based on latency tolerance
Grant 10,545,701 - Mathews , et al. Ja
2020-01-28
System and Method for Communication Link Management in a Credit-Based System
App 20200004700 - Mathews; Gregory S. ;   et al.
2020-01-02
Memory request management system
Grant 10,437,758 - Mathews , et al. O
2019-10-08
Systems and methods for dynamically switching memory performance states
Grant 10,175,905 - Jeter , et al. J
2019-01-08
Systems And Methods For Dynamically Switching Memory Performance States
App 20180074743 - Jeter; Robert E. ;   et al.
2018-03-15
Testing and error recovery across multiple switching fabrics
Grant 7,876,693 - Mathews , et al. January 25, 2
2011-01-25
Hierarchical rate limiting with proportional limiting
Grant 7,801,045 - Mathews , et al. September 21, 2
2010-09-21
Pointer allocation by prime numbers
Grant 7,733,888 - Mathews , et al. June 8, 2
2010-06-08
Flow control in a distributed scalable, shared memory switching fabric system
Grant 7,525,917 - Ferolito , et al. April 28, 2
2009-04-28
Hierarchical Rate Limiting With Proportional Limiting
App 20080316921 - Mathews; Gregory S. ;   et al.
2008-12-25
Using reassembly queue sets for packet reassembly
Grant 7,394,822 - Mathews , et al. July 1, 2
2008-07-01
Optimal load balancing across multiple switching fabrics
Grant 7,242,691 - Mathews , et al. July 10, 2
2007-07-10
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
App 20040139280 - Quach, Nhon T. ;   et al.
2004-07-15
Processing ordered data requests to a memory
Grant 6,725,339 - Fu , et al. April 20, 2
2004-04-20
Testing and error recovery across multiple switching fabrics
App 20040037277 - Mathews, Gregory S. ;   et al.
2004-02-26
Method and apparatus to provide advanced load ordering
Grant 6,681,317 - Mathews January 20, 2
2004-01-20
Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end
Grant 6,678,815 - Mathews , et al. January 13, 2
2004-01-13
Pointer allocation by prime numbers
App 20030235189 - Mathews, Gregory S. ;   et al.
2003-12-25
Flow control in a distributed scalable, shared memory switching fabric system
App 20030223448 - Ferolito, Philip ;   et al.
2003-12-04
Using reassembly queue sets for packet reassembly
App 20030223458 - Mathews, Gregory S. ;   et al.
2003-12-04
Optimal load balancing across multiple switching fabrics
App 20030223438 - Mathews, Gregory S. ;   et al.
2003-12-04
System and method for translation buffer accommodating multiple page sizes
App 20030196066 - Mathews, Gregory S.
2003-10-16
System and method for translation buffer accommodating multiple page sizes
Grant 6,625,715 - Mathews September 23, 2
2003-09-23
Method and apparatus for set associative cache tag error detection
Grant 6,567,952 - Quach , et al. May 20, 2
2003-05-20
TLB using region ID prevalidation
Grant 6,560,689 - Mathews , et al. May 6, 2
2003-05-06
Method and apparatus for managing temporal and non-temporal data in a single cache structure
Grant 6,542,966 - Crawford , et al. April 1, 2
2003-04-01
Hierarchical fully-associative-translation lookaside buffer structure
Grant 6,418,521 - Mathews , et al. July 9, 2
2002-07-09
Processing ordered data requests to a memory
App 20020073284 - Fu, John Wai Cheong ;   et al.
2002-06-13
Unaligned semaphore adder
Grant 6,405,233 - Mathews , et al. June 11, 2
2002-06-11
Processing Ordered Data Requests To A Memory
App 20010044881 - FU, JOHN WAI CHEONG ;   et al.
2001-11-22
Dual-ported, pipelined, two level cache system
Grant 6,272,597 - Fu , et al. August 7, 2
2001-08-07
Method and apparatus for managing a memory array
Grant 6,105,115 - Mathews , et al. August 15, 2
2000-08-15
Multi-processing cache coherency protocol on a local bus
Grant 5,802,577 - Bhat , et al. September 1, 1
1998-09-01
Method and apparatus for independently stopping and restarting functional units
Grant 5,634,131 - Matter , et al. May 27, 1
1997-05-27
Central processing unit address pipelining
Grant 5,469,544 - Aatresh , et al. November 21, 1
1995-11-21
Method and apparatus for reduced latency in hold bus cycles
Grant 5,398,244 - Mathews , et al. March 14, 1
1995-03-14
Method and apparatus for independently stopping and restarting functional units
Grant 5,392,437 - Matter , et al. February 21, 1
1995-02-21
Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only
Grant 5,359,723 - Mathews , et al. October 25, 1
1994-10-25

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