Masuda; Hiroo
Patent Applications and Registrations
Patent applications and USPTO patent grants for Masuda; Hiroo.The latest application filed is for "semiconductor memory device".
- Masuda; Hiroo - Tokyo JP
- Masuda; Hiroo - Kodaira JP
- Masuda; Hiroo - Nishitama JP
- Masuda; Hiroo - Kokubunji JA
| Patent | Date |
|---|---|
| Method of designing a semiconductor device Grant 6,949,387 - Miura , et al. September 27, 2 | 2005-09-27 |
| Semiconductor memory device App 20040214355 - Miura, Hideo ; et al. | 2004-10-28 |
| FET having a gate electrode of a honeycomb structure Grant 6,737,714 - Masuda , et al. May 18, 2 | 2004-05-18 |
| Calculating method for inductance in a semiconductor integrated circuit App 20040075436 - Kurokawa, Atsushi ; et al. | 2004-04-22 |
| Method of fabricating low stress semiconductor devices with thermal oxide isolation Grant 6,620,704 - Miura , et al. September 16, 2 | 2003-09-16 |
| Multi-layer wiring device, wiring method and wiring characteristic analyzing/predicting method App 20030161128 - Masuda, Hiroo | 2003-08-28 |
| Semiconductor device App 20030136984 - Masuda, Hiroo ; et al. | 2003-07-24 |
| Process variable identification method, process variable identification apparatus, and evaluation sample App 20030055618 - Masuda, Hiroo | 2003-03-20 |
| Low stress semiconductor devices with thermal oxide isolation App 20020093060 - Miura, Hideo ; et al. | 2002-07-18 |
| Semiconductor device and method of fabricating same Grant 6,337,517 - Ohta , et al. January 8, 2 | 2002-01-08 |
| Method of manufacturing an improved SOI (silicon-on-insulator) semiconductor integrated circuit device Grant 6,063,686 - Masuda , et al. May 16, 2 | 2000-05-16 |
| Process for producing a bipolar device Grant 5,643,805 - Ohta , et al. July 1, 1 | 1997-07-01 |
| Bipolar device and production thereof Grant 5,619,069 - Ohta , et al. April 8, 1 | 1997-04-08 |
| Semiconductor memory Grant 5,170,374 - Shimohigashi , et al. December 8, 1 | 1992-12-08 |
| Semiconductor memory Grant 4,860,255 - Shimohigashi , et al. August 22, 1 | 1989-08-22 |
| Electrically erasable programmable RAM Grant 4,656,607 - Hagiwara , et al. April 7, 1 | 1987-04-07 |
| Insulated gate field effect transistor Grant 4,656,492 - Sunami , et al. April 7, 1 | 1987-04-07 |
| Semiconductor memory Grant 4,592,022 - Shimohigashi , et al. May 27, 1 | 1986-05-27 |
| Semiconductor memory Grant 4,539,658 - Shimohigashi , et al. September 3, 1 | 1985-09-03 |
| Semiconductor memory Grant 4,472,792 - Shimohigashi , et al. September 18, 1 | 1984-09-18 |
| Programmable semiconductor integrated circuitry including a programming semiconductor element Grant 4,455,495 - Masuhara , et al. June 19, 1 | 1984-06-19 |
| Dynamic monolithic memory Grant 4,399,519 - Masuda , et al. August 16, 1 | 1983-08-16 |
| Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device Grant 4,086,642 - Yoshida , et al. April 25, 1 | 1978-04-25 |
| Semiconductor Device Grant 3,855,610 - Masuda , et al. December 17, 1 | 1974-12-17 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 