loadpatents
name:-0.010833978652954
name:-0.007606029510498
name:-0.0076210498809814
Maslennikov; Dmitry M. Patent Filings

Maslennikov; Dmitry M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Maslennikov; Dmitry M..The latest application filed is for "method to do control speculation on loads in a high performance strand-based loop accelerator".

Company Profile
4.5.11
  • Maslennikov; Dmitry M. - Moscow RU
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption
Grant 10,430,191 - Astigeyevich , et al. O
2019-10-01
Method to do control speculation on loads in a high performance strand-based loop accelerator
Grant 10,241,789 - Ostanevich , et al.
2019-03-26
Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator
Grant 10,241,801 - Iyer , et al.
2019-03-26
Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor
Grant 10,235,171 - Ostanevich , et al.
2019-03-19
Method And Apparatus To Efficiently Handle Allocation Of Memory Ordering Buffers In A Multi-strand Out-of-order Loop Processor
App 20180181397 - OSTANEVICH; Alexander Y. ;   et al.
2018-06-28
Method And Apparatus To Create Register Windows For Parallel Iterations To Achieve High Performance In Hw-sw Codesigned Loop Accelerator
App 20180181405 - IYER; Jayesh ;   et al.
2018-06-28
Method To Do Control Speculation On Loads In A High Performance Strand-based Loop Accelerator
App 20180181396 - OSTANEVICH; Alexander Y. ;   et al.
2018-06-28
Increasing Processor Instruction Window Via Seperating Instructions According To Criticality
App 20170161075 - TITOV; ALEXANDR ;   et al.
2017-06-08
Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations
App 20160378480 - Matveyev; Pavel G. ;   et al.
2016-12-29
Method And Apparatus For Non-speculative Fetch And Execution Of Control-dependent Blocks
App 20160055004 - GROCHOWSKI; EDWARD T. ;   et al.
2016-02-25
Methods And Apparatus To Compile Instructions For A Vector Of Instruction Pointers Processor Architecture
App 20150324200 - Astigeyevich; Yevgeniy M. ;   et al.
2015-11-12
Methods And Apparatus To Compile Instructions For A Vector Of Instruction Pointers Processor Architecture
App 20140281407 - Astigeyevich; Yevgeniy M. ;   et al.
2014-09-18
Compiler method and apparatus for elimination of redundant speculative computations from innermost loops
Grant 6,301,706 - Maslennikov , et al. October 9, 2
2001-10-09

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed