loadpatents
name:-0.011305093765259
name:-0.0088498592376709
name:-0.00037407875061035
Martinez; Muriel Patent Filings

Martinez; Muriel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Martinez; Muriel.The latest application filed is for "method for polishing heterostructures".

Company Profile
0.7.7
  • Martinez; Muriel - Saint Egreve FR
  • Martinez; Muriel - St. Egreve FR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Germanium layer polishing
Grant 8,304,345 - Martinez , et al. November 6, 2
2012-11-06
Method For Polishing Heterostructures
App 20110117740 - Martinez; Muriel ;   et al.
2011-05-19
Germanium Layer Polishing
App 20110045654 - Martinez; Muriel ;   et al.
2011-02-24
Planarization of a heteroepitaxial layer
Grant 7,718,534 - Martinez , et al. May 18, 2
2010-05-18
Substrate layer cutting device and method
Grant 7,406,994 - Martinez , et al. August 5, 2
2008-08-05
Semiconductor structure and method of making same
Grant 7,391,094 - Rayssac , et al. June 24, 2
2008-06-24
Substrate Layer Cutting Device And Method
App 20070122926 - Martinez; Muriel ;   et al.
2007-05-31
Planarization Of A Heteroepitaxial Layer
App 20070087570 - Martinez; Muriel ;   et al.
2007-04-19
Substrate layer cutting device and method
Grant 7,189,304 - Martinez , et al. March 13, 2
2007-03-13
Semiconductor structure and method of making same
App 20060086949 - Rayssac; Olivier ;   et al.
2006-04-27
Semiconductor structure and method of making same
Grant 6,989,314 - Rayssac , et al. January 24, 2
2006-01-24
Methods of producing a heterogeneous semiconductor structure
Grant 6,858,517 - Martinez , et al. February 22, 2
2005-02-22
Methods Of Producing A Heterogeneous Semiconductor Structure
App 20040253795 - Martinez, Muriel ;   et al.
2004-12-16
Substrate layer cutting device and method
App 20040144487 - Martinez, Muriel ;   et al.
2004-07-29

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