loadpatents
name:-0.041164875030518
name:-0.025777101516724
name:-0.014515161514282
Mark; William R. Patent Filings

Mark; William R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mark; William R..The latest application filed is for "convolutional neural network on programmable two dimensional image processor".

Company Profile
12.19.18
  • Mark; William R. - Mountain View CA
  • Mark; William R. - Austin TX US
  • Mark; William R. - Hillsboro OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
Grant 11,196,953 - Meixner , et al. December 7, 2
2021-12-07
Convolutional Neural Network On Programmable Two Dimensional Image Processor
App 20210004633 - Shacham; Ofer ;   et al.
2021-01-07
Convolutional neural network on programmable two dimensional image processor
Grant 10,789,505 - Shacham , et al. September 29, 2
2020-09-29
Macro I/O unit for image processor
Grant 10,733,956 - Meixner , et al.
2020-08-04
Architecture for high performance, power efficient, programmable image processing
Grant 10,719,905 - Zhu , et al.
2020-07-21
Macro I/O Unit for Image Processor
App 20200160809 - Meixner; Albert ;   et al.
2020-05-21
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register
App 20200154072 - Meixner; Albert ;   et al.
2020-05-14
Convolutional neural network on programmable two dimensional image processor
Grant 10,546,211 - Shacham , et al. Ja
2020-01-28
Compiler Techniques For Mapping Program Code To A High Performance, Power Efficient, Programmable Image Processing Hardware Plat
App 20200020069 - Meixner; Albert ;   et al.
2020-01-16
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
Grant 10,531,030 - Meixner , et al. J
2020-01-07
Architecture For High Performance, Power Efficient, Programmable Image Processing
App 20190378239 - Zhu; Qiuling ;   et al.
2019-12-12
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register
App 20190327437 - Meixner; Albert ;   et al.
2019-10-24
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
Grant 10,387,988 - Meixner , et al. A
2019-08-20
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
Grant 10,387,989 - Meixner , et al. A
2019-08-20
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
Grant 10,334,194 - Meixner , et al.
2019-06-25
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register
App 20180234653 - Meixner; Albert ;   et al.
2018-08-16
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
Grant 9,986,187 - Meixner , et al. May 29, 2
2018-05-29
Architecture for high performance, power efficient, programmable image processing
Grant 9,965,824 - Zhu , et al. May 8, 2
2018-05-08
Convolutional Neural Network On Programmable Two Dimensional Image Processor
App 20180005074 - SHACHAM; Ofer ;   et al.
2018-01-04
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register
App 20180007303 - Meixner; Albert ;   et al.
2018-01-04
Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
App 20180007302 - MEIXNER; Albert ;   et al.
2018-01-04
Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
App 20180005346 - MEIXNER; Albert ;   et al.
2018-01-04
Convolutional Neural Network On Programmable Two Dimensional Image Processor
App 20180005075 - Shacham; Ofer ;   et al.
2018-01-04
Compiler Techniques For Mapping Program Code To A High Performance, Power Efficient, Programmable Image Processing Hardware Platform
App 20170287103 - Meixner; Albert ;   et al.
2017-10-05
Compiler Techniques for Mapping Program Code to a High Performance, Power Efficient, Programmable Image Processing Hardware Platform
App 20170249716 - MEIXNER; Albert ;   et al.
2017-08-31
Architecture For High Performance, Power Efficient, Programmable Image Processing
App 20160314555 - Zhu; Qiuling ;   et al.
2016-10-27
Multiresolution ray intersection
Grant 8,379,026 - Stoll , et al. February 19, 2
2013-02-19
System and method for computing intersections between rays and surfaces
Grant 7,567,248 - Mark , et al. July 28, 2
2009-07-28
Subshader mechanism for programming language
Grant 7,463,259 - Kolb , et al. December 9, 2
2008-12-09
Multiresolution ray intersection
App 20080159651 - Stoll; Gordon W. ;   et al.
2008-07-03
System and method for interfacing graphics program modules
Grant 7,268,785 - Glanville , et al. September 11, 2
2007-09-11
Capturing both digital and analog forms of a signal through the same probing path
Grant 6,847,199 - Kaufman , et al. January 25, 2
2005-01-25
Multi-channel, low input capacitance signal probe and probe head
Grant 6,781,391 - Reed , et al. August 24, 2
2004-08-24
Capturing both digital and analog forms of a signal through the same probing path
App 20030160625 - Kaufman, A. Roy ;   et al.
2003-08-28
Multi-channel, low input capacitance signal probe and probe head
App 20030107388 - Reed, Gary W. ;   et al.
2003-06-12
Latched electrical connector
Grant 5,915,987 - Reed , et al. June 29, 1
1999-06-29

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