MANUSHAROW; Mathew J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for MANUSHAROW; Mathew J..The latest application filed is for "size and efficiency of dies".

Company Profile

24.62.87

MANUSHAROW; Mathew J. - Phoenix AZ
Manusharow; Mathew J - Phoenix AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Size And Efficiency Of Dies App 20220115326 - MANUSHAROW; Mathew J. ; et al.	2022-04-14
High Performance Integrated Rf Passives Using Dual Lithography Process App 20220102261 - ELSHERBINI; Adel A. ; et al.	2022-03-31
High Density Interconnect Device And Method App 20220028790 - Roy; Mihir K. ; et al.	2022-01-27
High performance integrated RF passives using dual lithography process Grant 11,227,825 - Elsherbini , et al. January 18, 2	2022-01-18
High density interconnect device and method Grant 11,158,578 - Roy , et al. October 26, 2	2021-10-26
Helical Plated Through-hole Package Inductor App 20210304952 - Lambert; William J. ; et al.	2021-09-30
Method of making an inductor Grant 10,998,120 - Lambert , et al. May 4, 2	2021-05-04
Package power delivery using plane and shaped vias Grant 10,971,416 - Bharath , et al. April 6, 2	2021-04-06
Size And Efficiency Of Dies App 20210043572 - Manusharow; Mathew J. ; et al.	2021-02-11
Improving size and efficiency of dies Grant 10,886,228 - Manusharow , et al. January 5, 2	2021-01-05
Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same Grant 10,847,467 - Collins , et al. November 24, 2	2020-11-24
Rlink--die to die channel interconnect configurations to improve signaling Grant 10,784,204 - Aygun , et al. Sept	2020-09-22
Substrate conductor structure and method Grant 10,734,282 - Chase , et al.	2020-08-04
High Density Interconnect Device And Method App 20200111745 - Roy; Mihir K. ; et al.	2020-04-09
Rlink - Die To Die Channel Interconnect Configurations To Improve Signaling App 20200066641 - AYGUN; Kemal ; et al.	2020-02-27
Power-delivery Methods For Embedded Multi-die Interconnect Bridges And Methods Of Assembling Same App 20200051916 - COLLINS; Andrew ; et al.	2020-02-13
Integrated circuit package substrate Grant 10,522,455 - Manusharow , et al. Dec	2019-12-31
Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same Grant 10,490,503 - Collins , et al. Nov	2019-11-26
Package Power Delivery Using Plane And Shaped Vias App 20190355636 - Bharath; Krishna ; et al.	2019-11-21
Microprocessor package with first level die bump ground webbing structure Grant 10,453,795 - Zhang , et al. Oc	2019-10-22
High density interconnect device and method Grant 10,446,499 - Roy , et al. Oc	2019-10-15
Power-delivery Methods For Embedded Multi-die Interconnect Bridges And Methods Of Assembling Same App 20190304911 - Collins; Andrew ; et al.	2019-10-03
Package power delivery using plane and shaped vias Grant 10,410,939 - Bharath , et al. Sept	2019-09-10
Inductor formed in substrate Grant 10,312,007 - Roy , et al.	2019-06-04
Integrated Circuit Package Substrate App 20190164881 - MANUSHAROW; Mathew J. ; et al.	2019-05-30
Integrated circuit package substrate Grant 10,242,942 - Manusharow , et al.	2019-03-26
Helical Plated Through-hole Package Inductor App 20190051447 - Lambert; William J. ; et al.	2019-02-14
Substrate Conductor Structure And Method App 20190027405 - Chase; Harold Ryan ; et al.	2019-01-24
Package-integrated microchannels Grant 10,186,465 - Eid , et al. Ja	2019-01-22
Helical plated through-hole package inductor Grant 10,163,557 - Lambert , et al. Dec	2018-12-25
Size And Efficiency Of Dies App 20180331042 - Manusharow; Mathew J. ; et al.	2018-11-15
Microprocessor Package With First Level Die Bump Ground Webbing Structure App 20180331035 - ZHANG; Yu Amos ; et al.	2018-11-15
Improved Package Power Delivery Using Plane And Shaped Vias App 20180331003 - BHARATH; Krishna ; et al.	2018-11-15
Vertically Embedded Passive Components App 20180332708 - LAMBERT; William J. ; et al.	2018-11-15
Substrate conductor structure and method Grant 10,121,701 - Chase , et al. November 6, 2	2018-11-06
High Performance Integrated Rf Passives Using Dual Lithography Process App 20180315690 - ELSHERBINI; Adel A. ; et al.	2018-11-01
Direct chip attach using embedded traces Grant 10,085,341 - Roy , et al. September 25, 2	2018-09-25
Package-integrated Microchannels App 20180226310 - EID; Feras ; et al.	2018-08-09
Electrical Interconnect Formed Through Buildup Process App 20180213655 - Roy; Mihir K. ; et al.	2018-07-26
Bridge interconnect with air gap in package assembly Grant 10,008,451 - Chiu , et al. June 26, 2	2018-06-26
Systems and methods for controlled effective series resistance component Grant 9,992,871 - Lambert , et al. June 5, 2	2018-06-05
Hybrid pitch package with ultra high density interconnect capability Grant 9,899,311 - Manusharow , et al. February 20, 2	2018-02-20
Electronic package and method of connecting a first die to a second die to form an electronic package Grant 9,741,686 - Chase , et al. August 22, 2	2017-08-22
Bridge Interconnect With Air Gap In Package Assembly App 20170221828 - Chiu; Chia-Pin ; et al.	2017-08-03
Shielded bundle interconnect App 20170187419 - Zhang; Yu ; et al.	2017-06-29
Direct Chip Attach Using Embedded Traces App 20170188460 - Roy; Mihir K. ; et al.	2017-06-29
Helical Plated Through-hole Package Inductor App 20170178786 - Lambert; William J. ; et al.	2017-06-22
High Density Interconnect Device And Method App 20170162509 - Roy; Mihir K. ; et al.	2017-06-08
Integrated Circuit Package Substrate App 20170154842 - MANUSHAROW; Mathew J. ; et al.	2017-06-01
Systems And Methods For Controlled Effective Series Resistance Component App 20170135211 - Lambert; William J. ; et al.	2017-05-11
Hybrid pitch package with ultra high density interconnect capability Grant 9,633,938 - Manusharow , et al. April 25, 2	2017-04-25
Method of forming a circuit board Grant 9,622,350 - Roy , et al. April 11, 2	2017-04-11
Package Integrated Power Inductors Using Lithographically Defined Vias App 20170092412 - Manusharow; Mathew J. ; et al.	2017-03-30
Hybrid Pitch Package With Ultra High Density Interconnect Capability App 20170092573 - MANUSHAROW; Mathew J. ; et al.	2017-03-30
Hybrid Pitch Package With Ultra High Density Interconnect Capability App 20170092575 - Manusharow; Mathew J. ; et al.	2017-03-30
Bridge interconnect with air gap in package assembly Grant 9,589,866 - Chiu , et al. March 7, 2	2017-03-07
Weaved Electrical Components In A Substrate Package Core App 20170027062 - ROY; MIHIR K. ; et al.	2017-01-26
Landside stiffening capacitors to enable ultrathin and other low-Z products Grant 9,552,977 - Roy , et al. January 24, 2	2017-01-24
Suspended inductor microelectronic structures Grant 9,526,175 - Manusharow , et al. December 20, 2	2016-12-20
Weaved electrical components in a substrate package core Grant 9,521,751 - Roy , et al. December 13, 2	2016-12-13
Substrate Conductor Structure And Method App 20160336223 - Chase; Harold Ryan ; et al.	2016-11-17
Package for a microelectronic die, microelectronic assembly containing same, microelectronic system, and method of reducing die stress in a microelectronic package Grant 9,478,476 - Mallik , et al. October 25, 2	2016-10-25
Substrate conductor structure and method Grant 9,406,587 - Chase , et al. August 2, 2	2016-08-02
Bridge Interconnect With Air Gap In Package Assembly App 20160204049 - Chiu; Chia-Pin ; et al.	2016-07-14
Electronic Package And Method Of Connecting A First Die To A Second Die To Form An Electronic Package App 20160204067 - Chase; Harold Ryan ; et al.	2016-07-14
Bridge interconnect with air gap in package assembly Grant 9,275,971 - Chiu , et al. March 1, 2	2016-03-01
Electronic package and method of connecting a first die to a second die to form an electronic package Grant 9,275,975 - Chase , et al. March 1, 2	2016-03-01
Forming in-situ micro-feature structures with coreless packages Grant 9,214,439 - Nalla , et al. December 15, 2	2015-12-15
Non-cylindrical conducting shapes in multilayer laminated substrate cores Grant 9,198,293 - Chase , et al. November 24, 2	2015-11-24
Electronic Package And Method Of Connecting A First Die To A Second Die To Form An Electronic Package App 20150279813 - Chase; Harold Ryan ; et al.	2015-10-01
In situ-built pin-grid arrays for coreless substrates, and methods of making same Grant 9,111,916 - Roy , et al. August 18, 2	2015-08-18
Weaved Electrical Components In A Substrate Package Core App 20150138743 - ROY; Mihir K. ; et al.	2015-05-21
Direct Chip Attach Using Embedded Traces App 20150092378 - ROY; Mihir K. ; et al.	2015-04-02
In situ-built pin-grid arrays for coreless substrates, and methods of making same Grant 8,952,540 - Roy , et al. February 10, 2	2015-02-10
High Density Interconnect Device And Method App 20150035144 - Roy; Mihir K. ; et al.	2015-02-05
Bridge Interconnect With Air Gap In Package Assembly App 20150011050 - Chiu; Chia-Pin ; et al.	2015-01-08
Forming In-situ Micro-feature Structures With Coreless Packages App 20140367843 - Nalla; Ravi K. ; et al.	2014-12-18
Direct external interconnect for embedded interconnect bridge package Grant 8,901,748 - Manusharow , et al. December 2, 2	2014-12-02
Microelectronic package and method of manufacturing same Grant 8,896,116 - Nalla , et al. November 25, 2	2014-11-25
Bridge interconnect with air gap in package assembly Grant 8,872,349 - Chiu , et al. October 28, 2	2014-10-28
High density interconnect device and method Grant 8,866,308 - Roy , et al. October 21, 2	2014-10-21
Direct External Interconnect For Embedded Interconnect Bridge Package App 20140264791 - MANUSHAROW; MATHEW J. ; et al.	2014-09-18
Suspended Inductor Microelectronic Structures App 20140251669 - Manusharow; Mathew J. ; et al.	2014-09-11
Bumpless build-up layer and laminated core hybrid structures and methods of assembling same Grant 8,809,124 - Manusharow , et al. August 19, 2	2014-08-19
Non-cylindrical Conducting Shapes In Multilayer Laminated Substrate Cores App 20140197545 - Chase; Harold R. ; et al.	2014-07-17
Forming in-situ micro-feature structures with coreless packages Grant 8,772,924 - Nalla , et al. July 8, 2	2014-07-08
In Situ-built Pin-grid Arrays For Coreless Substrates, And Methods Of Making Same App 20140179060 - Roy; Mihir K. ; et al.	2014-06-26
High Density Interconnect Device And Method App 20140175636 - Roy; Mihir K. ; et al.	2014-06-26
Electrical Interconnect Formed Through Buildup Process App 20140166353 - Roy; Mihir K. ; et al.	2014-06-19
Landside Stiffening Capacitors To Enable Ultrathin And Other Low-z Products App 20140160675 - Roy; Mihir K. ; et al.	2014-06-12
Inductor Formed In Substrate App 20140159850 - Roy; Mihir K. ; et al.	2014-06-12
Bridge Interconnect With Air Gap In Package Assembly App 20140070380 - Chiu; Chia-Pin ; et al.	2014-03-13
Bumpless Build-up Layer And Laminated Core Hybrid Structures And Methods Of Assembling Same App 20130344662 - Manusharow; Mathew J. ; et al.	2013-12-26
Substrate Conductor Structure And Method App 20130341772 - Chase; Harold Ryan ; et al.	2013-12-26
Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby Grant 8,580,616 - Nalla , et al. November 12, 2	2013-11-12
Package For A Microelectronic Die, Microelectronic Assembly Containing Same, Microelectronic System, And Method Of Reducing Die Stress In A Microelectronic Package App 20130270691 - Mallik; Debendra ; et al.	2013-10-17
Low-profile Microelectronic Package, Method Of Manufacturing Same, And Electronic Assembly Containing Same App 20130228911 - Manusharow; Mathew J. ; et al.	2013-09-05
Forming In-situ Micro-feature Structures With Coreless Packages App 20130214403 - Nalla; Ravi ; et al.	2013-08-22
Bumpless build-up layer and laminated core hybrid structures and methods of assembling same Grant 8,508,037 - Manusharow , et al. August 13, 2	2013-08-13
Microelectronic Package And Method Of Manufacturing Same App 20130119544 - Nalla; Ravi K. ; et al.	2013-05-16
Forming in-situ micro-feature structures with coreless packages Grant 8,431,438 - Nalla , et al. April 30, 2	2013-04-30
In Situ-built Pin-grid Arrays For Coreless Substrates, And Methods Of Making Same App 20130001794 - Roy; Mihir K. ; et al.	2013-01-03
Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby Grant 8,304,913 - Nalla , et al. November 6, 2	2012-11-06
Low-profile Microelectronic Package, Method Of Manufacturing Same, And Electronic Assembly Containing Same App 20120139095 - Manusharow; Mathew J. ; et al.	2012-06-07
Bumpless Build-up Layer And Laminated Core Hybrid Structures And Methods Of Assembling Same App 20120139116 - Manusharow; Mathew J. ; et al.	2012-06-07
Methods Of Forming Fully Embedded Bumpless Build-up Layer Packages And Structures Formed Thereby App 20120074580 - Nalla; Ravi K. ; et al.	2012-03-29
Microelectronic Package And Method Of Manufacturing Same App 20110316140 - Nalla; Ravi K. ; et al.	2011-12-29
Forming In-situ Micro-feature Structures With Coreless Packages App 20110241195 - Nalla; Ravi K. ; et al.	2011-10-06
Microelectronic package and method of manufacturing same App 20110108999 - Nalla; Ravi K. ; et al.	2011-05-12
Multiple-dice packages using elements between dice to control application of underfill material to reduce void formation Grant 7,589,395 - Sathe , et al. September 15, 2	2009-09-15
Multiple-dice Packages With Controlled Underfill And Methods Of Manufacture App 20080001310 - Sathe; Ajit V. ; et al.	2008-01-03

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